Add a new Verilog test for Vivado simulation

d983c430 · Javier D. Garcia-Lasheras · 583bd9e0 · d983c430 · d983c430
Commit d983c430 authored Mar 13, 2017 by Javier D. Garcia-Lasheras
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vivado.py hdlmake/tools/vivado.py +1 -1

Manifest.py tests/counter/sim/vivado/verilog/Manifest.py +9 -0

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--- a/hdlmake/tools/vivado.py
+++ b/hdlmake/tools/vivado.py
@@ -64,7 +64,7 @@ class ToolVivado(ToolXilinx, ToolSim):
                               "$(PROJECT).cache", "$(PROJECT).data", "work",
                               "$(PROJECT).runs", "$(PROJECT).hw", "xsim.dir",
                               "$(PROJECT).ip_user_files", "$(PROJECT_FILE)"],
-                     'mrproper': ["*.wdb"]}
+                     'mrproper': ["*.wdb", "*.vcd"]}

    TCL_CONTROLS = {'bitstream': '$(TCL_OPEN)\n'
                                 'launch_runs impl_1 -to_step write_bitstream'

--- a/tests/counter/sim/vivado/verilog/Manifest.py
+++ b/tests/counter/sim/vivado/verilog/Manifest.py
+action = "simulation"
+sim_tool = "vivado"
+sim_top = "counter_tb"
+
+sim_post_cmd = "xsim %s -gui" % sim_top
+
+modules = {
+  "local" : [ "../../../testbench/counter_tb/verilog" ],
+}