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Hdlmake
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368df9d9
Commit
368df9d9
authored
Dec 06, 2019
by
Severin Haas
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Added test/example stuff for Verilog synthesis of IGLOO2 devices.
parent
3eaa0599
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Manifest.py
tests/counter/syn/igloo2_libero/verilog/Manifest.py
+15
-0
Manifest.py
tests/counter/top/igloo2/verilog/Manifest.py
+9
-0
igloo2_top.v
tests/counter/top/igloo2/verilog/igloo2_top.v
+31
-0
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tests/counter/syn/igloo2_libero/verilog/Manifest.py
0 → 100644
View file @
368df9d9
target
=
"microsemi"
syn_tool
=
"liberosoc"
action
=
"synthesis"
language
=
"verilog"
syn_family
=
"IGLOO2"
syn_device
=
"M2GL060"
syn_grade
=
"-1"
syn_package
=
"484 FBGA"
syn_top
=
"igloo2_top"
syn_project
=
"demo"
modules
=
{
"local"
:
[
"../../../top/igloo2/verilog"
],
}
tests/counter/top/igloo2/verilog/Manifest.py
0 → 100644
View file @
368df9d9
files
=
[
"igloo2_top.v"
,
"../igloo2_top.pdc"
,
"../igloo2_top.sdc"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/verilog"
],
}
tests/counter/top/igloo2/verilog/igloo2_top.v
0 → 100644
View file @
368df9d9
//---------------------------------------------------------------------
// Design : Counter verilog top module, Microsemi IGLOO2 M2GL060
// Author : Javier D. Garcia-Lasheras, small changes by Severin Haas
//---------------------------------------------------------------------
module
igloo2_top
(
clear_i
,
count_i
,
clock_i
,
led_o
)
;
input
clear_i
,
count_i
,
clock_i
;
output
[
7
:
0
]
led_o
;
wire
s_clock
,
s_clear
,
s_count
;
wire
[
7
:
0
]
s_Q
;
counter
u1
(
.
clock
(
s_clock
)
,
.
clear
(
s_clear
)
,
.
count
(
s_count
)
,
.
Q
(
s_Q
)
)
;
assign
s_clock
=
clock_i
;
assign
s_clear
=
clear_i
;
assign
s_count
=
count_i
;
assign
led_o
[
7
:
0
]
=
s_Q
[
7
:
0
]
;
endmodule
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