GN4124 core - Release 2.0
dev_mcattin) to test the new features.
(red) Foreseen release, early adopters can use the development branch (Sources
- "HDL sources":
Interface (entity) changes
- Additional generic:
-
g_ACK_TIMEOUT, positive
: Used to set the ACk wait timeout (in wishbone clock cycles).
-
- Additional ports:
-
csr_err_i, std_logic
: Used to terminate the wishbone cycle if asserted. -
csr_rty_i, std_logic
: Not used. Reserved for future use. -
csr_int_i, std_logic
: Not used. Reserved for future use. -
dma_err_i, std_logic
: Not used. Reserved for future use. -
dma_rty_i, std_logic
: Not used. Reserved for future use. -
dma_int_i, std_logic
: Not used. Reserved for future use.
-
Release date
- 01 March 2014
04 February 2014