added by Erik van der Bij on 2014-02-05 10:42:30.899387
A new release of the Gennum PCIe interface chip to Wishbone core has
been made. The most important change is that if one addresses a
non-existant location, the core will reply with 0xFFFFFFFF instead of
making your system freeze.
Actually it is a
for which we like to receive feedback within a month time.
Note that the entity slightly changed, therefore the designs using the
GN4124 core have to be modified.
05-01-2012: Gennum allows open publishing of modified cores
added by Erik van der Bij on 2012-01-05 17:14:25.345327
CERN has adapted for its particular applications the original GN4124
VHDL and Verilog examples from Gennum. Alan Hutton, Gennum director of
Global Distribution Sales & Marketing, has given CERN the green light to
publish this modified code as open source.
Gennum just likes the references to Gennum be removed from the original
code. Of course Gennum cannot support this modified code, but they will
have their usual support and Tim Fairfield's blog (link no longer available).
CERN's PFC card on Gennum's blog
added by Anonymous on 2011-03-16 09:29:23.999150
CERN's PFC card and the Gennum to Wishbone core is featured on Gennum's
GN4124 Design blog (link no longer available)
Gennum core tested on the SPEC and PFC boards.
added by Anonymous on 2011-02-28 10:01:25.758240
The Gennum core has been tested on the SPEC and the PFC boards.
Both CSR and DMA wishbone interfaces works well.
Beta version ready!
added by Anonymous on 2010-11-11 13:37:11.168853
The beta version has been tested on a Gullwing development board from
For testing purpose, one 8KB RAM is connected as a slave on the DMA
Two slaves are connected to the CSR wishbone. One contains four status
registers, three with fixed values and one with the state of the
on-board DEBUG switches. The other slave have four control registers and
one of them is controlling the on-board LEDs.
First DMA transfer in both directions
added by Anonymous on 2010-10-21 08:59:15.962995
A first bi-directional DMA transfer has been achieved on the Gullwing
The interrupt message generation (MSI) is also working fine.