Q*: The SPEC board uses bank 1 of the XC6SLX45T FPGA to connect to
the GN4124. The SPEXI board
will use bank 1 and bank 5 of the XC6SLX100T to make this same
connection because bank 1 is too small to fit all connections. As I
understand the GN4142 it uses a IP core inside the FPGA to interface the
GN4124 with the internal FPGA design.
Are there any restrictions or constraints which limit or specify which
signal should be connected to which FPGA pin?
The reason why I’m asking this is because some IP cores make a fairly
restricted use of the FPGA resources to guarantee timing. I don’t know
if the GN4142 IP core locks certain I/O pins.
A*: The GN4124 core uses a BUFPLL to clock the local bus interface
signals. According to the Spartan-6 FPGA Clocking Resources User
page 28, bank 1 and bank 5 are in the same BUFPLL region. Therefore they
should be no problem using those two banks.
But anyway read carefully this user guide to make sure that this is
valid for your particular FPGA type/package. The Spartan6 clocking
scheme can be surprising sometimes!
Which repository to use?
Q*: Which sources to get in the SVN repository to use the core with a
A*: The SVN repository is deprecated. Please use the GIT repository
Please check the Releases page to learn about the supported
The core source files are in "/hdl/gn4124core/rtl". One can have a look
at the "Manifest.py" file to see what are the dependencies.
What can cause a DMA error?
Q*: What can cause the DMA engine to end up in ERROR state?
A*: The causes that leads to a DMA error are:
1) Start a DMA with a length of 0.
2) Trying to start a DMA when one is still in progress.
3) The DMA engine received a read completion without data.
Note that to exit the ERROR state a new DMA transfer must be started.
What is the theoretical maximum data transfer rate?
The maximum Gennum local interface (interface with the FPGA) clock
frequency is 200MHz,
with 16-bit data transfer on both edges (DDR).
Therefore the maximum data transfer rate is:
2byte * 2 * 200MHz => 800MB/s
Then subtracting the packet header over-head:
Packet header size = 8 bytes
Packet max payload size = 128 bytes (constant defined in the hdl core,
c_L2P_MAX_PAYLOAD in l2p_dma_master.vhd)
The effective maximum data transfer is:
(800 * 128)/(128 + 8) => 752.94MB/s
Note:* No real measurement of the data transfer rate have been
realised so far.