First draft for GN4124 core technical specification.
This specification describes how the core works internally. For each
internal block, we give a summary description of its
This block takes the double data rate 16-bit P2L (PCI Express to Local
Bus direction) bus from the GN4124 device and converts it to a single
data rate 32-bit bus for use inside the GN4124 core.
It takes the internal single data rate 32 bit data and transmits it as
double data rate 16-bit data on the L2P (Local Bus to PCI Express
This block extracts header information, address, data, byte enables, and
timing controls of the packets from the GN4124 chip. It provides signals
type of packet (target read request, target write request,master
read completion ...)
Begin of packet
Address that will increment with data
End of packet
The Wishbone master implements a master for the Wishbone interconnection
bus. It transforms a PCIe write into a Wishbone write and a PCIe read
into a Wishbone read. Only single word reads and writes are supported.
PCI express bursts are divided in single reads and writes.
Data are coming from the packet decoder. Wishbone signals are generated
and the master waits for an acknowledge. The incoming requests are saved
in a FIFO. The FIFO depth is 16. The Wishbone master is allowing the
GN4124 chip to send a request only if the FIFO is empty. The latency of
the transfer between the GN4124 chip and the Wishbone master makes this
Arbitrate between Wishbone master, DMA master and DMA sequencer. The
arbiter is waiting for a request signal from one of this blocks and it
grants the bus to the first requester until the end of the packet.
The highest priority is for Wishbone master and the lower priority is
for the DMA
Interrupt clock bridge
It transforms input interrupt one-tick-long pulse clocked by sys_clk_i
in a one-tick-long pulse clocked by the GN4124 local bus clock.