Important changes include:

1. Clear separation of resets per clock domain (with the exception
   of the wbgen-generated dma controller registers).

2. Conversion of all processes to use synchronous resets when the
   reset is synced with the clock of the process.

3. Use of standard synchronizers from general-cores when crossing
   clock-domains.

Due to the change in processes to use sync resets, a lot of code
has changed indentation. To this end, it might be useful to perform
a case insensitive diff when studying the changes of this commit.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>