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Gennum GN4124 core
Commit 0284a69b authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: DMA rewrite work-in-progress.

parent f1e9a982
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general-cores @ b9925c97
Subproject commit 64f7e518bab2bf0489077f4b9eb26e8cccbf1411 Subproject commit b9925c97707698310e232ae2736e3d3d4b1b5971
hdl/rtl/l2p_dma_master.vhd
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hdl/rtl/p2l_dma_master.vhd
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hdl/rtl/spartan6/gn4124_core.vhd
View file @ 0284a69b
...@@ -52,9 +52,8 @@ entity gn4124_core is ...@@ -52,9 +52,8 @@ entity gn4124_core is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110; g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128; g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 64;
g_P2L_FIFO_FULL_THRES : positive := 500; g_L2P_FIFO_SIZE : positive := 128;
g_L2P_DATA_FIFO_SIZE : positive := 128;
-- Wishbone ACK timeout (in wishbone clock cycles) -- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT : positive := 100); g_ACK_TIMEOUT : positive := 100);
port ( port (
...@@ -289,19 +288,6 @@ architecture rtl of gn4124_core is ...@@ -289,19 +288,6 @@ architecture rtl of gn4124_core is
signal dma_irq : std_logic; signal dma_irq : std_logic;
attribute keep of dma_ctrl_l2p_error : signal is "TRUE";
attribute keep of dma_ctrl_l2p_done : signal is "TRUE";
attribute keep of dma_ctrl_start_l2p : signal is "TRUE";
attribute keep of dma_ctrl_abort : signal is "TRUE";
attribute keep of ldm_arb_valid : signal is "TRUE";
attribute keep of ldm_arb_dframe : signal is "TRUE";
attribute keep of ldm_arb_data : signal is "TRUE";
attribute keep of ldm_arb_req : signal is "TRUE";
attribute keep of l2p_rdy : signal is "TRUE";
attribute keep of l_wr_rdy : signal is "TRUE";
attribute keep of tx_error : signal is "TRUE";
attribute keep of arb_ldm_gnt : signal is "TRUE";
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- CSR wishbone bus -- CSR wishbone bus
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -313,14 +299,8 @@ architecture rtl of gn4124_core is ...@@ -313,14 +299,8 @@ architecture rtl of gn4124_core is
signal l2p_dma_in : t_wishbone_master_in; signal l2p_dma_in : t_wishbone_master_in;
signal l2p_dma_out : t_wishbone_master_out; signal l2p_dma_out : t_wishbone_master_out;
signal p2l_dma_adr : std_logic_vector(31 downto 0); signal p2l_dma_in : t_wishbone_master_in;
signal p2l_dma_dat : std_logic_vector(31 downto 0); signal p2l_dma_out : t_wishbone_master_out;
signal p2l_dma_sel : std_logic_vector(3 downto 0);
signal p2l_dma_cyc : std_logic;
signal p2l_dma_stb : std_logic;
signal p2l_dma_we : std_logic;
signal p2l_dma_ack : std_logic;
signal p2l_dma_stall : std_logic;
--============================================================================== --==============================================================================
-- Architecture begin (gn4124_core) -- Architecture begin (gn4124_core)
...@@ -619,7 +599,7 @@ begin ...@@ -619,7 +599,7 @@ begin
cmp_l2p_dma_master : entity work.l2p_dma_master cmp_l2p_dma_master : entity work.l2p_dma_master
generic map ( generic map (
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK, g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_DATA_FIFO_SIZE => g_L2P_DATA_FIFO_SIZE, g_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_BYTE_SWAP => TRUE) g_BYTE_SWAP => TRUE)
port map ( port map (
clk_i => sys_clk, clk_i => sys_clk,
...@@ -660,10 +640,9 @@ begin ...@@ -660,10 +640,9 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
cmp_p2l_dma_master : entity work.p2l_dma_master cmp_p2l_dma_master : entity work.p2l_dma_master
generic map ( generic map (
--g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK, g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE => g_P2L_FIFO_SIZE, g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES, g_BYTE_SWAP => TRUE)
g_BYTE_SWAP => TRUE)
port map ( port map (
clk_i => sys_clk, clk_i => sys_clk,
rst_n_i => sys_rst_n, rst_n_i => sys_rst_n,
...@@ -699,17 +678,10 @@ begin ...@@ -699,17 +678,10 @@ begin
pdm_arb_req_o => pdm_arb_req, pdm_arb_req_o => pdm_arb_req,
arb_pdm_gnt_i => arb_pdm_gnt, arb_pdm_gnt_i => arb_pdm_gnt,
p2l_dma_rst_n_i => dma_rst_n_i, wb_dma_rst_n_i => wb_dma_rst_n,
p2l_dma_clk_i => dma_clk_i, wb_dma_clk_i => wb_dma_clk,
p2l_dma_adr_o => p2l_dma_adr, wb_dma_i => p2l_dma_in,
p2l_dma_dat_i => dma_dat_i, wb_dma_o => p2l_dma_out,
p2l_dma_dat_o => p2l_dma_dat,
p2l_dma_sel_o => p2l_dma_sel,
p2l_dma_cyc_o => p2l_dma_cyc,
p2l_dma_stb_o => p2l_dma_stb,
p2l_dma_we_o => p2l_dma_we,
p2l_dma_ack_i => p2l_dma_ack,
p2l_dma_stall_i => p2l_dma_stall,
next_item_carrier_addr_o => next_item_carrier_addr, next_item_carrier_addr_o => next_item_carrier_addr,
next_item_host_addr_h_o => next_item_host_addr_h, next_item_host_addr_h_o => next_item_host_addr_h,
...@@ -721,9 +693,12 @@ begin ...@@ -721,9 +693,12 @@ begin
next_item_valid_o => next_item_valid next_item_valid_o => next_item_valid
); );
p2l_dma_in.dat <= dma_dat_i;
p2l_dma_in.err <= dma_err_i;
p2l_dma_in.rty <= dma_rty_i;
p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i, p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i,
l2p_dma_out, p2l_dma_adr, p2l_dma_cyc, p2l_dma_dat, l2p_dma_out, p2l_dma_out)
p2l_dma_sel, p2l_dma_stb, p2l_dma_we)
begin begin
if (dma_ctrl_direction = '0') then if (dma_ctrl_direction = '0') then
dma_adr_o <= l2p_dma_out.adr; dma_adr_o <= l2p_dma_out.adr;
...@@ -734,17 +709,17 @@ begin ...@@ -734,17 +709,17 @@ begin
dma_we_o <= l2p_dma_out.we; dma_we_o <= l2p_dma_out.we;
l2p_dma_in.ack <= dma_ack_i; l2p_dma_in.ack <= dma_ack_i;
l2p_dma_in.stall <= dma_stall_i; l2p_dma_in.stall <= dma_stall_i;
p2l_dma_ack <= '0'; p2l_dma_in.ack <= '0';
p2l_dma_stall <= '0'; p2l_dma_in.stall <= '0';
else else
dma_adr_o <= p2l_dma_adr; dma_adr_o <= p2l_dma_out.adr;
dma_dat_o <= p2l_dma_dat; dma_dat_o <= p2l_dma_out.dat;
dma_sel_o <= p2l_dma_sel; dma_sel_o <= p2l_dma_out.sel;
dma_cyc_o <= p2l_dma_cyc; dma_cyc_o <= p2l_dma_out.cyc;
dma_stb_o <= p2l_dma_stb; dma_stb_o <= p2l_dma_out.stb;
dma_we_o <= p2l_dma_we; dma_we_o <= p2l_dma_out.we;
p2l_dma_ack <= dma_ack_i; p2l_dma_in.ack <= dma_ack_i;
p2l_dma_stall <= dma_stall_i; p2l_dma_in.stall <= dma_stall_i;
l2p_dma_in.ack <= '0'; l2p_dma_in.ack <= '0';
l2p_dma_in.stall <= '0'; l2p_dma_in.stall <= '0';
end if; end if;
......
hdl/rtl/spartan6/gn4124_core_pkg.vhd
View file @ 0284a69b
...@@ -61,9 +61,8 @@ package gn4124_core_pkg is ...@@ -61,9 +61,8 @@ package gn4124_core_pkg is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110; g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128; g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 64;
g_P2L_FIFO_FULL_THRES : positive := 500; g_L2P_FIFO_SIZE : positive := 128;
g_L2P_DATA_FIFO_SIZE : positive := 128;
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED; g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE; g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED; g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
...@@ -122,9 +121,8 @@ package gn4124_core_pkg is ...@@ -122,9 +121,8 @@ package gn4124_core_pkg is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110; g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128; g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 64;
g_P2L_FIFO_FULL_THRES : positive := 500; g_L2P_FIFO_SIZE : positive := 128;
g_L2P_DATA_FIFO_SIZE : positive := 128;
g_ACK_TIMEOUT : positive := 100); g_ACK_TIMEOUT : positive := 100);
port ( port (
--------------------------------------------------------- ---------------------------------------------------------
......
hdl/rtl/spartan6/xwb_gn4124_core.vhd
View file @ 0284a69b
...@@ -45,9 +45,8 @@ entity xwb_gn4124_core is ...@@ -45,9 +45,8 @@ entity xwb_gn4124_core is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110; g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128; g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 64;
g_P2L_FIFO_FULL_THRES : positive := 500; g_L2P_FIFO_SIZE : positive := 128;
g_L2P_DATA_FIFO_SIZE : positive := 128;
-- WB config for three WB interfaces -- WB config for three WB interfaces
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED; g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE; g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
...@@ -204,8 +203,7 @@ begin ...@@ -204,8 +203,7 @@ begin
g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE, g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE,
g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES, g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES,
g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE, g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_P2L_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES, g_L2P_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_L2P_DATA_FIFO_SIZE => g_L2P_DATA_FIFO_SIZE,
g_ACK_TIMEOUT => g_ACK_TIMEOUT) g_ACK_TIMEOUT => g_ACK_TIMEOUT)
port map ( port map (
rst_n_a_i => rst_n_a_i, rst_n_a_i => rst_n_a_i,
......
hdl/sim/example_tb/main.sv
View file @ 0284a69b
...@@ -54,13 +54,13 @@ module main; ...@@ -54,13 +54,13 @@ module main;
logic wb_dma_clk; logic wb_dma_clk;
logic wb_dma_rst_n; logic wb_dma_rst_n;
initial begin initial begin
rst_125m_n = 0; rst_125m_n = 0;
rst_62m5_n = 0; rst_62m5_n = 0;
#80ns; #80ns;
rst_125m_n = 1; rst_125m_n = 1;
rst_62m5_n = 1; rst_62m5_n = 1;
end end
IGN4124PCIMaster i_gn4124 (); IGN4124PCIMaster i_gn4124 ();
...@@ -71,8 +71,8 @@ module main; ...@@ -71,8 +71,8 @@ module main;
) )
DUT ( DUT (
.rst_n_a_i (i_gn4124.rst_n), .rst_n_a_i (i_gn4124.rst_n),
.clk_200m_o (clk_gn4124), .clk_200m_o (clk_gn4124),
.rst_200m_n_o (rst_gn4124_n), .rst_200m_n_o (rst_gn4124_n),
.p2l_clk_p_i (i_gn4124.p2l_clk_p), .p2l_clk_p_i (i_gn4124.p2l_clk_p),
.p2l_clk_n_i (i_gn4124.p2l_clk_n), .p2l_clk_n_i (i_gn4124.p2l_clk_n),
.p2l_data_i (i_gn4124.p2l_data), .p2l_data_i (i_gn4124.p2l_data),
...@@ -114,16 +114,17 @@ module main; ...@@ -114,16 +114,17 @@ module main;
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_gn4124; assign wb_dma_clk = clk_gn4124;
assign wb_dma_rst_n = rst_gn4124_n; assign wb_dma_rst_n = rst_gn4124_n;
-----/\----- EXCLUDED -----/\----- */
assign wb_dma_clk = clk_125m; assign wb_dma_clk = clk_125m;
assign wb_dma_rst_n = rst_125m_n; assign wb_dma_rst_n = rst_125m_n;
-----/\----- EXCLUDED -----/\----- */ /* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_62m5; assign wb_dma_clk = clk_62m5;
assign wb_dma_rst_n = rst_62m5_n; assign wb_dma_rst_n = rst_62m5_n;
-----/\----- EXCLUDED -----/\----- */
xwb_dpram # xwb_dpram #
( (
.g_size (32), .g_size (16384),
.g_init_file ("mem_init.bram"),
.g_slave1_interface_mode (1), // 1 = PIPELINED .g_slave1_interface_mode (1), // 1 = PIPELINED
.g_slave2_interface_mode (1), .g_slave2_interface_mode (1),
.g_slave1_granularity (1), // 1 = WORD .g_slave1_granularity (1), // 1 = WORD
...@@ -179,7 +180,7 @@ module main; ...@@ -179,7 +180,7 @@ module main;
initial begin initial begin
automatic int ntest = 1; automatic int ntest = 1;
const int tests = 9; const int tests = 11;
uint32_t addr, val, expected; uint32_t addr, val, expected;
...@@ -191,6 +192,7 @@ module main; ...@@ -191,6 +192,7 @@ module main;
@(posedge clk_125m); @(posedge clk_125m);
// ---------------------------------
$write("Test %0d/%0d: simple read/write accesses over Wishbone: ", $write("Test %0d/%0d: simple read/write accesses over Wishbone: ",
ntest++, tests); ntest++, tests);
...@@ -209,9 +211,11 @@ module main; ...@@ -209,9 +211,11 @@ module main;
acc.write(addr, 'h0); acc.write(addr, 'h0);
end end
repeat(2) @(posedge clk_125m);
$write("PASS\n"); $write("PASS\n");
/* -----\/----- EXCLUDED -----\/----- // ---------------------------------
$write("Test %0d/%0d: 128B read over DMA, abort after first read: ", $write("Test %0d/%0d: 128B read over DMA, abort after first read: ",
ntest++, tests); ntest++, tests);
...@@ -221,15 +225,8 @@ module main; ...@@ -221,15 +225,8 @@ module main;
acc.write('h14, 'h80); // count acc.write('h14, 'h80); // count
acc.write('h00, 'h01); // start acc.write('h00, 'h01); // start
// Check values read from memory // wait for transfer to start
@(posedge i_gn4124.l2p_valid); // skip header @(posedge i_gn4124.l2p_valid);
repeat(2) @(posedge i_gn4124.l2p_clk_p);
expected = 32'h8000001f;
val = i_gn4124.l2p_data;
@(posedge i_gn4124.l2p_clk_n);
val |= i_gn4124.l2p_data << 16;
val_check("DMA read-back", 'h20, val, expected);
repeat(2) @(posedge clk_125m); repeat(2) @(posedge clk_125m);
...@@ -241,14 +238,42 @@ module main; ...@@ -241,14 +238,42 @@ module main;
repeat(2) @(posedge clk_125m); repeat(2) @(posedge clk_125m);
$write("PASS\n"); $write("PASS\n");
-----/\----- EXCLUDED -----/\----- */
$write("Test %0d/%0d: 2x128B chained reads over DMA: ", // ---------------------------------
$write("Test %0d/%0d: 256B DMA write: ",
ntest++, tests);
// Setup data in BFM memory
for (addr = 'h00; addr < 'h40; addr += 1)
i_gn4124.host_mem_write(4 * addr, 32'h80000020 - addr);
// Setup DMA
acc.write('h14, 'h100); // count
acc.write('h20, 'h01); // attrib
acc.write('h0c, 'h20000000); // hstartL
acc.write('h10, 'h00000000); // hstartH
acc.write('h00, 'h01); // start
@(posedge dma_irq);
check_irq_status;
clear_irq;
repeat(4) @(posedge clk_125m);
$write("PASS\n");
// wait for WB transfer to finish
#5us;
// ---------------------------------
$write("Test %0d/%0d: 2x128B chained DMA reads: ",
ntest++, tests); ntest++, tests);
// Setup DMA chain info in BFM memory // Setup DMA chain info in BFM memory
i_gn4124.host_mem_write('h20000, 'h00001000); // remote address i_gn4124.host_mem_write('h20000, 'h00000080); // remote address
i_gn4124.host_mem_write('h20004, 'h20000100); // hstartL i_gn4124.host_mem_write('h20004, 'h20000080); // hstartL
i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH
i_gn4124.host_mem_write('h2000C, 'h80); // count i_gn4124.host_mem_write('h2000C, 'h80); // count
i_gn4124.host_mem_write('h20010, 'h00); // nextL i_gn4124.host_mem_write('h20010, 'h00); // nextL
...@@ -271,11 +296,10 @@ module main; ...@@ -271,11 +296,10 @@ module main;
check_irq_status; check_irq_status;
clear_irq; clear_irq;
for (addr = 'h00; addr < 'h20; addr += 1) for (addr = 'h00; addr < 'h40; addr += 1)
begin begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1; expected = 32'h80000020 - addr;
mem_check(4 * addr, expected); mem_check(4 * addr, expected);
mem_check('h100 + 4 * addr, expected);
end end
repeat(4) @(posedge clk_125m); repeat(4) @(posedge clk_125m);
...@@ -283,7 +307,7 @@ module main; ...@@ -283,7 +307,7 @@ module main;
$write("PASS\n"); $write("PASS\n");
// --------------------------------- // ---------------------------------
$write("Test %0d/%0d: 256B read over DMA: ", $write("Test %0d/%0d: 256B DMA read: ",
ntest++, tests); ntest++, tests);
// Setup DMA // Setup DMA
...@@ -301,7 +325,7 @@ module main; ...@@ -301,7 +325,7 @@ module main;
for (addr = 'h00; addr < 'h40; addr += 1) for (addr = 'h00; addr < 'h40; addr += 1)
begin begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1; expected = 32'h80000020 - addr;
mem_check(4 * addr, expected); mem_check(4 * addr, expected);
end end
...@@ -309,16 +333,57 @@ module main; ...@@ -309,16 +333,57 @@ module main;
$write("PASS\n"); $write("PASS\n");
// ---------------------------------
$write("Test %0d/%0d: 2x4KiB chained DMA write: ",
ntest++, tests);
// Setup data in BFM memory
for (addr = 'h00; addr < 'h800; addr += 1)
i_gn4124.host_mem_write(4 * addr, 32'h80000020 - addr);
// Setup DMA chain info in BFM memory
i_gn4124.host_mem_write('h20000, 'h00001000); // remote address
i_gn4124.host_mem_write('h20004, 'h20001000); // hstartL
i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH
i_gn4124.host_mem_write('h2000C, 'h1000); // count
i_gn4124.host_mem_write('h20010, 'h00); // nextL
i_gn4124.host_mem_write('h20014, 'h00); // nextH
i_gn4124.host_mem_write('h20018, 'h01); // attrib
// Setup DMA
acc.write('h14, 'h1000); // count
acc.write('h20, 'h03); // attrib
acc.write('h0c, 'h20000000); // hstartL
acc.write('h10, 'h00000000); // hstartH
// Point to chain info in BFM memory
acc.write('h18, 'h20020000); // nextL
acc.write('h1C, 'h00000000); // nextH
acc.write('h00, 'h01); // start
@(posedge dma_irq);
check_irq_status;
clear_irq;
repeat(4) @(posedge clk_125m);
$write("PASS\n");
// wait for WB transfer to finish
#5us;
// Check all four byte swap settings // Check all four byte swap settings
// --------------------------------- // ---------------------------------
for (int i = 0; i < 4; i++) begin for (int i = 0; i < 4; i++) begin
$write("Test %0d/%0d: 16KB read over DMA (byte swap = %0d): ", $write("Test %0d/%0d: 8KiB DMA read (byte swap = %0d): ",
ntest++, tests, i); ntest++, tests, i);
// Restart // Restart
acc.write('h14, 'h4000); // count acc.write('h14, 'h2000); // count
acc.write('h20, 'h00); // attrib acc.write('h20, 'h00); // attrib
acc.write('h0c, 'h20000000 + i * 'h4000); // hstartL acc.write('h0c, 'h20000000); // hstartL
acc.write('h10, 'h00000000); // hstartH acc.write('h10, 'h00000000); // hstartH
acc.write('h00, (i << 2) | 'h01); // start acc.write('h00, (i << 2) | 'h01); // start
...@@ -326,16 +391,16 @@ module main; ...@@ -326,16 +391,16 @@ module main;
check_irq_status; check_irq_status;
for (addr = 'h00; addr < 'h1000; addr += 1) for (addr = 'h00; addr < 'h800; addr += 1)
begin begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1; expected = 32'h80000020 - addr;
if (i == 1) if (i == 1)
expected = {<<8{expected}}; expected = {<<8{expected}};
else if (i == 2) else if (i == 2)
expected = {<<16{expected}}; expected = {<<16{expected}};
else if (i == 3) else if (i == 3)
expected = {<<16{{<<8{expected}}}}; expected = {<<16{{<<8{expected}}}};
mem_check((i * 'h4000) + 4 * addr, expected); mem_check(4 * addr, expected);
end end
clear_irq; clear_irq;
...@@ -347,26 +412,26 @@ module main; ...@@ -347,26 +412,26 @@ module main;
#1us; #1us;
end end
$write("Test %0d/%0d: 8KB read over DMA with 32bit host address overflow: ", $write("Test %0d/%0d: 256B DMA read with 32bit host address overflow: ",
ntest++, tests); ntest++, tests);
acc.write('h14, 'h2000); // count acc.write('h14, 'h100); // count
acc.write('h20, 'h00); // attrib acc.write('h20, 'h00); // attrib
acc.write('h0c, 'hfffff000); // hstartL acc.write('h0c, 'hffffff80); // hstartL
acc.write('h10, 'h00000000); // hstartH acc.write('h10, 'h00000000); // hstartH
acc.write('h00, 'h01); // start acc.write('h00, 'h01); // start
// Transfer will be split internally by L2P DMA master in two requests, the first // Transfer will be split internally by L2P DMA master in two requests, the first
// one with a 32-bit adress starting at ffff_f000 and the next one with a 64-bit // one with a 32-bit adress starting at ffff_ff80 and the next one with a 64-bit
// address starting at 1_0000_0000 // address starting at 1_0000_0000
@(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe); @(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow header", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h02ff0000); val_check("Host address overflow header", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h02ff0020);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow address", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'hfffff000); val_check("Host address overflow address", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'hffffff80);
@(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe); @(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow header", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h03ff0000); val_check("Host address overflow header", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h03ff0020);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow address high", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 1); val_check("Host address overflow address high", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 1);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
......
hdl/sim/example_tb/mem_init.bram deleted 100644 → 0
View file @ f1e9a982
10000000000000000000000000011111
10000000000000000000000000011110
10000000000000000000000000011101
10000000000000000000000000011100
10000000000000000000000000011011
10000000000000000000000000011010
10000000000000000000000000011001
10000000000000000000000000011000
10000000000000000000000000010111
10000000000000000000000000010110
10000000000000000000000000010101
10000000000000000000000000010100
10000000000000000000000000010011
10000000000000000000000000010010
10000000000000000000000000010001
10000000000000000000000000010000
10000000000000000000000000001111
10000000000000000000000000001110
10000000000000000000000000001101
10000000000000000000000000001100
10000000000000000000000000001011
10000000000000000000000000001010
10000000000000000000000000001001
10000000000000000000000000001000
10000000000000000000000000000111
10000000000000000000000000000110
10000000000000000000000000000101
10000000000000000000000000000100
10000000000000000000000000000011
10000000000000000000000000000010
10000000000000000000000000000001
10000000000000000000000000000000
hdl/sim/example_tb/wave.do
View file @ 0284a69b
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_dout
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/dma_packet_len
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/clk_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/target_addr_cnt
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/pd_pdm_data_valid_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/pd_pdm_data_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_wr_d
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_din_d
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_full
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/p2l_rdy_o
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_clk_i
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_empty
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_rd
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_dout
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_valid
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_o
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_clk_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_cyc_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_stb_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_we_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_ack_o
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_adr_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_abort_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_error_i
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_done_i
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_irq_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_direction_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_carrier_addr_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_h_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_l_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_len_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap_o
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {537831000 ps} 0} WaveRestoreCursors {{Cursor 1} {6339711 ps} 0} {{Cursor 2} {129899342 ps} 1}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 199 configure wave -namecolwidth 277
configure wave -valuecolwidth 100 configure wave -valuecolwidth 210
configure wave -justifyvalue left configure wave -justifyvalue left
configure wave -signalnamewidth 1 configure wave -signalnamewidth 1
configure wave -snapdistance 10 configure wave -snapdistance 10
...@@ -31,4 +72,4 @@ configure wave -griddelta 40 ...@@ -31,4 +72,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ps configure wave -timelineunits ps
update update
WaveRestoreZoom {0 ps} {737045400 ps} WaveRestoreZoom {0 ps} {24072512 ps}
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