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Gennum GN4124 core
Commit 0284a69b authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: DMA rewrite work-in-progress.

parent f1e9a982
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general-cores @ b9925c97
Subproject commit 64f7e518bab2bf0489077f4b9eb26e8cccbf1411
Subproject commit b9925c97707698310e232ae2736e3d3d4b1b5971
hdl/rtl/l2p_dma_master.vhd
View file @ 0284a69b
......@@ -6,7 +6,8 @@
--
-- unit name: l2p_dma_master
--
-- description: L2P DMA master
-- description: 32 bit L2P DMA master. Provides a pipelined wishbone interface
-- that performs DMA transfer from the local application to PCI express host.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2020
......@@ -34,7 +35,7 @@ use work.genram_pkg.all;
entity l2p_dma_master is
generic (
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_DATA_FIFO_SIZE : positive := 128;
g_FIFO_SIZE : positive := 128;
g_BYTE_SWAP : boolean := FALSE);
port (
-- GN4124 core clk and reset
......@@ -76,21 +77,32 @@ end l2p_dma_master;
architecture arch of l2p_dma_master is
-- Used to tweak the almost full flag threshold of the SYNC FIFO
-- in
-- in order to help with timing by giving an advanced warning
-- that we can then pipeline through an equal number of registers.
constant c_SYNC_FIFO_FULL_DELAY : natural := 3;
type l2p_dma_state_type is (L2P_IDLE, L2P_SETUP, L2P_WAIT,
L2P_HEADER, L2P_HOLD, L2P_ADDR_H,
L2P_ADDR_L, L2P_DATA, L2P_NEXT,
L2P_ERROR);
-- Even though the actual limit is 4KiB, the GN4124 really hates it
-- if we try to send more than 256 Bytes (64 Words) within a single packet.
-- During tests, we've seen that the GN4124 chip might freeze when such
-- a request arrives, with the probability of a freeze increasing with
-- the size of the packet.
-- The overhead of the extra transaction is minimal so we keep here the
-- limit that was there in previous versions of this code (128 Bytes,
-- or 32 Words).
constant c_L2P_MAX_PAYLOAD : integer := 32;
type l2p_dma_state_type is (L2P_IDLE, L2P_WB_SETUP, L2P_SETUP,
L2P_WAIT, L2P_HEADER, L2P_HOLD,
L2P_ADDR_H, L2P_ADDR_L, L2P_DATA,
L2P_NEXT, L2P_ERROR);
signal l2p_dma_current_state : l2p_dma_state_type := L2P_IDLE;
type wb_dma_state_type is (WB_IDLE, WB_SETUP, WB_DATA, WB_HOLD);
type wb_dma_state_type is (WB_IDLE, WB_SETUP, WB_DATA, WB_HOLD);
signal wb_dma_current_state : wb_dma_state_type := WB_IDLE;
signal dma_target_addr : unsigned(29 downto 0) := (others => '0');
signal dma_total_len : unsigned(29 downto 0) := (others => '0');
signal dma_packet_len : unsigned(10 downto 0) := (others => '0');
signal dma_packet_len : unsigned(5 downto 0) := (others => '0');
signal dma_host_addr : unsigned(63 downto 0) := (others => '0');
signal dma_byte_swap : std_logic_vector(1 downto 0) := (others => '0');
......@@ -104,29 +116,30 @@ architecture arch of l2p_dma_master is
signal l2p_fsm_hold : std_logic := '0';
signal l2p_fsm_data : std_logic_vector(31 downto 0) := (others => '0');
signal l2p_fsm_dma_param_wr : std_logic := '0';
signal l2p_fsm_dma_param_busy : std_logic := '0';
signal dma_param_sync : std_logic_vector(40 downto 0) := (others => '0');
signal dma_param_wr : std_logic := '0';
signal l2p_fsm_dma_param_wr : std_logic := '0';
signal l2p_fsm_dma_param_busy : std_logic := '0';
signal dma_param_sync : std_logic_vector(59 downto 0) := (others => '0');
signal dma_param_wr : std_logic := '0';
signal l2p_timeout_cnt : unsigned(12 downto 0) := (others => '0');
signal dma_last_packet : std_logic := '0';
signal wb_dma_cyc : std_logic := '0';
signal wb_dma_stb : std_logic := '0';
signal wb_dma_addr : unsigned(29 downto 0) := (others => '0');
signal wb_dma_addr_d : unsigned(29 downto 0) := (others => '0');
signal wb_dma_cnt_stb : unsigned(10 downto 0) := (others => '0');
signal wb_dma_cnt_ack : unsigned(10 downto 0) := (others => '0');
signal wb_dma_cnt_stb : unsigned(29 downto 0) := (others => '0');
signal wb_dma_cnt_ack : unsigned(29 downto 0) := (others => '0');
signal wb_dma_fsm_en : std_logic := '0';
signal wb_dma_fsm_en_sync : std_logic := '0';
signal data_fifo_rd : std_logic := '0';
signal data_fifo_wr : std_logic := '0';
signal data_fifo_empty : std_logic := '1';
signal data_fifo_full : std_logic := '0';
signal data_fifo_din : std_logic_vector(31 downto 0) := (others => '0');
signal data_fifo_dout : std_logic_vector(31 downto 0) := (others => '0');
signal data_fifo_rd : std_logic := '0';
signal data_fifo_wr : std_logic := '0';
signal data_fifo_empty : std_logic := '1';
signal data_fifo_full : std_logic := '0';
signal data_fifo_din : std_logic_vector(31 downto 0) := (others => '0');
signal data_fifo_dout : std_logic_vector(31 downto 0) := (others => '0');
signal data_fifo_dout_d : std_logic_vector(31 downto 0) := (others => '0');
signal fsm_fifo_rst_n : std_logic := '0';
......@@ -155,22 +168,23 @@ begin
l2p_edb_o <= '0';
fsm_fifo_rst_n <= '0';
data_fifo_rd <= '0';
l2p_fsm_dma_param_wr <= '0';
else
data_fifo_dout_d <= data_fifo_dout;
-- default values if not overriden by current state
ldm_arb_req_o <= '0';
l2p_fsm_valid <= '0';
l2p_fsm_dframe <= '0';
l2p_fsm_dma_param_wr <= '0';
dma_ctrl_done_o <= '0';
dma_ctrl_error_o <= '0';
l2p_edb_o <= '0';
fsm_fifo_rst_n <= '1';
data_fifo_rd <= '0';
wb_dma_fsm_en <= '1';
l2p_timeout_cnt <= (others => '0');
ldm_arb_req_o <= '0';
l2p_fsm_valid <= '0';
l2p_fsm_dframe <= '0';
l2p_fsm_dma_param_wr <= l2p_fsm_dma_param_busy;
dma_ctrl_done_o <= '0';
dma_ctrl_error_o <= '0';
l2p_edb_o <= '0';
fsm_fifo_rst_n <= '1';
data_fifo_rd <= '0';
wb_dma_fsm_en <= '1';
l2p_timeout_cnt <= (others => '0');
case l2p_dma_current_state is
......@@ -185,26 +199,31 @@ begin
dma_host_addr_l <= unsigned(dma_ctrl_host_addr_l_i);
dma_total_len <= unsigned(dma_ctrl_len_i(31 downto 2));
dma_byte_swap <= dma_ctrl_byte_swap_i;
l2p_dma_current_state <= L2P_WB_SETUP;
end if;
when L2P_WB_SETUP =>
l2p_fsm_dma_param_wr <= '1';
if l2p_fsm_dma_param_busy = '1' then
l2p_dma_current_state <= L2P_SETUP;
end if;
when L2P_SETUP =>
-- Calculate DMA packet length for next tranfer. A transfer can be
-- up to 1024 words, limited by the "length" field in the L2P header.
if dma_total_len > 1024 then
dma_packet_len <= to_unsigned(1024, dma_packet_len'length);
-- We limit it artificially to c_L2P_MAX_PAYLOAD (see note in
-- constant declaration).
if dma_total_len > c_L2P_MAX_PAYLOAD then
dma_packet_len <= to_unsigned(c_L2P_MAX_PAYLOAD, dma_packet_len'length);
dma_last_packet <= '0';
elsif dma_total_len = 1024 then
dma_packet_len <= to_unsigned(1024, dma_packet_len'length);
elsif dma_total_len = c_L2P_MAX_PAYLOAD then
dma_packet_len <= to_unsigned(c_L2P_MAX_PAYLOAD, dma_packet_len'length);
dma_last_packet <= '1';
else
dma_packet_len <= dma_total_len(10 downto 0);
dma_packet_len <= dma_total_len(5 downto 0);
dma_last_packet <= '1';
end if;
l2p_fsm_dma_param_wr <= '1';
if l2p_fsm_dma_param_busy = '1' then
l2p_dma_current_state <= L2P_WAIT;
end if;
l2p_dma_current_state <= L2P_WAIT;
when L2P_WAIT =>
-- Send request to DMA arbiter
......@@ -237,7 +256,7 @@ begin
-- FBE (First Byte Enable)
l2p_fsm_data(19 downto 16) <= "1111";
-- Length field (in 32 bit words). When zero it means 1024 words.
l2p_fsm_data(9 downto 0) <= std_logic_vector(dma_packet_len(9 downto 0));
l2p_fsm_data(9 downto 0) <= "0000" & std_logic_vector(dma_packet_len);
if (l2p_64b_address = '1') then
l2p_dma_current_state <= L2P_ADDR_H;
else
......@@ -260,10 +279,10 @@ begin
l2p_dma_current_state <= L2P_DATA;
when L2P_HOLD =>
l2p_fsm_dframe <= '1';
l2p_fsm_valid <= '0';
l2p_fsm_dframe <= '1';
l2p_fsm_valid <= '0';
if data_fifo_empty = '0' and l2p_rdy_i = '1' then
data_fifo_rd <= '1';
data_fifo_rd <= '1';
l2p_dma_current_state <= L2P_DATA;
end if;
......@@ -281,6 +300,7 @@ begin
if dma_packet_len = 1 then
l2p_fsm_dframe <= '0';
if dma_last_packet = '0' then
data_fifo_rd <= '0';
l2p_dma_current_state <= L2P_NEXT;
else
dma_total_len <= (others => '0');
......@@ -301,12 +321,10 @@ begin
end if;
when L2P_NEXT =>
if data_fifo_empty = '1' then
dma_total_len <= dma_total_len - 1024;
dma_target_addr <= dma_target_addr + 1024;
dma_host_addr <= dma_host_addr + 4096;
l2p_dma_current_state <= L2P_SETUP;
end if;
dma_total_len <= dma_total_len - c_L2P_MAX_PAYLOAD;
dma_target_addr <= dma_target_addr + c_L2P_MAX_PAYLOAD;
dma_host_addr <= dma_host_addr + 4*c_L2P_MAX_PAYLOAD;
l2p_dma_current_state <= L2P_SETUP;
when L2P_ERROR =>
wb_dma_fsm_en <= '0';
......@@ -332,15 +350,15 @@ begin
-------------------------------------------------
gen_sync_word_dma_param : if g_DMA_USE_PCI_CLK = FALSE generate
signal dma_param_to_sync : std_logic_vector(40 downto 0);
signal dma_param_to_sync : std_logic_vector(59 downto 0);
begin
dma_param_to_sync(40 downto 11) <= std_logic_vector(dma_target_addr);
dma_param_to_sync(10 downto 0) <= std_logic_vector(dma_packet_len);
dma_param_to_sync(59 downto 30) <= std_logic_vector(dma_target_addr);
dma_param_to_sync(29 downto 0) <= std_logic_vector(dma_total_len);
cmp_sync_dma_param : entity work.gc_sync_word_wr
generic map (
g_AUTO_WR => false,
g_WIDTH => 41)
g_AUTO_WR => FALSE,
g_WIDTH => 60)
port map (
clk_in_i => clk_i,
rst_in_n_i => '1',
......@@ -362,46 +380,15 @@ begin
end generate gen_sync_word_dma_param;
gen_no_sync_word_dma_param: if g_DMA_USE_PCI_CLK = TRUE generate
dma_param_sync(40 downto 11) <= std_logic_vector(dma_target_addr);
dma_param_sync(10 downto 0) <= std_logic_vector(dma_packet_len);
gen_no_sync_word_dma_param : if g_DMA_USE_PCI_CLK = TRUE generate
dma_param_sync(59 downto 30) <= std_logic_vector(dma_target_addr);
dma_param_sync(29 downto 0) <= std_logic_vector(dma_total_len);
l2p_fsm_dma_param_busy <= l2p_fsm_dma_param_wr;
dma_param_wr <= l2p_fsm_dma_param_wr;
wb_dma_fsm_en_sync <= wb_dma_fsm_en;
end generate gen_no_sync_word_dma_param;
-- p_wb_master : process (wb_dma_clk_i) is
-- begin
-- if rising_edge(wb_dma_clk_i) then
-- if wb_dma_rst_n_i = '0' then
-- wb_dma_stb <= '0';
-- else
-- -- Handle strobe and address generation.
-- wb_dma_stb <= '0';
-- if wb_xfer_en_sync = '1' then
-- if wb_dma_cnt > 1 and data_fifo_full = '0' or
-- wb_dma_stb <= '1';
-- if wb_dma_i.stall = '0' and wb_dma_stb = '1' then
-- wb_dma_addr <= wb_dma_addr + 1;
-- wb_dma_cnt <= wb_dma_cnt - 1;
-- end if;
-- end if;
-- elsif dma_param_wr = '1' then
-- wb_dma_addr <= unsigned(dma_param_sync(40 downto 11));
-- wb_dma_cnt <= unsigned(dma_param_sync(10 downto 0));
-- end if;
-- -- Write received data to FIFO.
-- -- No need to check FIFO full, it was done earlier
-- -- when we decided to strobe.
-- data_fifo_din <= wb_dma_i.dat;
-- data_fifo_wr <= wb_dma_i.ack;
-- end if;
-- end if;
-- end process p_wb_master;
-- P2P communication, no need to drop WB cycle.
wb_dma_o.cyc <= '1';
wb_dma_o.cyc <= wb_dma_cyc;
wb_dma_o.stb <= wb_dma_stb;
wb_dma_o.adr <= "00" & std_logic_vector(wb_dma_addr_d);
wb_dma_o.we <= '0';
......@@ -418,6 +405,7 @@ begin
begin
if rising_edge(wb_dma_clk_i) then
if wb_dma_rst_n_i = '0' or wb_dma_fsm_en_sync = '0' then
wb_dma_cyc <= '0';
wb_dma_stb <= '0';
wb_dma_addr <= (others => '0');
wb_dma_current_state <= WB_IDLE;
......@@ -427,6 +415,7 @@ begin
-- default values if not overriden by current state
wb_dma_stb <= '0';
wb_dma_cyc <= '0';
case wb_dma_current_state is
......@@ -436,14 +425,15 @@ begin
end if;
when WB_SETUP =>
wb_dma_addr <= unsigned(dma_param_sync(40 downto 11));
wb_dma_cnt_stb <= unsigned(dma_param_sync(10 downto 0));
wb_dma_cnt_ack <= unsigned(dma_param_sync(10 downto 0));
wb_dma_addr <= unsigned(dma_param_sync(59 downto 30));
wb_dma_cnt_stb <= unsigned(dma_param_sync(29 downto 0));
wb_dma_cnt_ack <= unsigned(dma_param_sync(29 downto 0));
if data_fifo_full = '0' then
wb_dma_current_state <= WB_DATA;
end if;
when WB_DATA =>
wb_dma_cyc <= '1';
if wb_dma_i.ack = '1' then
wb_dma_cnt_ack <= wb_dma_cnt_ack - 1;
end if;
......@@ -452,14 +442,17 @@ begin
elsif wb_dma_cnt_ack = 0 and wb_dma_cnt_stb = 0 then
wb_dma_current_state <= WB_IDLE;
else
if wb_dma_i.stall = '0' and wb_dma_cnt_stb > 0 then
if wb_dma_cnt_stb > 0 then
wb_dma_stb <= '1';
wb_dma_addr <= wb_dma_addr + 1;
wb_dma_cnt_stb <= wb_dma_cnt_stb - 1;
if wb_dma_i.stall = '0' then
wb_dma_addr <= wb_dma_addr + 1;
wb_dma_cnt_stb <= wb_dma_cnt_stb - 1;
end if;
end if;
end if;
when WB_HOLD =>
wb_dma_cyc <= '1';
if wb_dma_i.ack = '1' then
wb_dma_cnt_ack <= wb_dma_cnt_ack - 1;
end if;
......@@ -474,15 +467,17 @@ begin
end if;
end if;
end process p_wb_fsm;
-----------------------------------------
-- Flow Control FIFO (cross-clock domain)
-----------------------------------------
-----------------------------------------
-- Flow Control FIFO (cross-clock domain)
-----------------------------------------
gen_sync_fifo : if g_DMA_USE_PCI_CLK = TRUE generate
signal data_fifo_full_d : std_logic_vector(c_SYNC_FIFO_FULL_DELAY - 1 downto 0) := (others => '0');
signal data_fifo_full_next : std_logic;
signal data_fifo_rst_n : std_logic := '0';
begin
p_fifo_full_delay_reg : process (clk_i) is
begin
if rising_edge(clk_i) then
......@@ -503,13 +498,12 @@ begin
cmp_data_fifo : generic_sync_fifo
generic map (
g_DATA_WIDTH => 32,
g_SIZE => 256,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_EMPTY => TRUE,
g_WITH_FULL => FALSE,
g_WITH_ALMOST_EMPTY => FALSE,
g_WITH_ALMOST_FULL => TRUE,
g_ALMOST_FULL_THRESHOLD => 128 - c_SYNC_FIFO_FULL_DELAY,
g_ALMOST_FULL_THRESHOLD => g_FIFO_SIZE/2 - c_SYNC_FIFO_FULL_DELAY,
g_REGISTER_FLAG_OUTPUTS => FALSE,
g_WITH_COUNT => FALSE)
port map (
......@@ -577,11 +571,12 @@ begin
cmp_data_fifo : generic_async_fifo_dual_rst
generic map (
g_DATA_WIDTH => 32,
g_SIZE => 256,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_WR_FULL => FALSE,
g_WITH_WR_ALMOST_FULL => TRUE,
g_ALMOST_FULL_THRESHOLD => 128 - c_SYNC_FIFO_FULL_DELAY)
-- 1 less for advance warning to WB FSM
g_ALMOST_FULL_THRESHOLD => g_FIFO_SIZE/2 - c_SYNC_FIFO_FULL_DELAY)
port map (
-- write port
rst_wr_n_i => data_fifo_rst_wr_n,
......
hdl/rtl/p2l_dma_master.vhd
View file @ 0284a69b
......@@ -7,11 +7,18 @@
-- unit name: p2l_dma_master
--
-- description: 32 bit P2L DMA master. Provides a pipelined Wishbone interface
-- to performs DMA transfers from PCI express host to local application.
-- that performs DMA transfers from PCI express host to local application.
-- This entity is also used to catch the next item in chained DMA.
--
-- IMPORTANT NOTE: This module has a known bug, where the FSM will consider a
-- transfer complete and signal the "done" to the DMA controller module without
-- waiting for the WB side to write all data. This can be a problem, especially
-- when the WB side is slower and the next DMA transaction is a read which will
-- switch the WB signals to the L2P module, thus cutting the previous WB write
-- transfer from this module in the middle.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2018
-- Copyright CERN 2010-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -27,15 +34,16 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
entity p2l_dma_master is
generic (
g_FIFO_SIZE : positive := 512;
g_FIFO_FULL_THRES : positive := 500;
-- Enable byte swap module (if false, no swap)
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_FIFO_SIZE : positive := 64;
g_BYTE_SWAP : boolean := FALSE);
port (
---------------------------------------------------------
......@@ -86,18 +94,11 @@ entity p2l_dma_master is
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_rst_n_i : in std_logic; -- Active low reset in sync with p2l_dma_clk_i
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(31 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
-- DMA Interface (Pipelined Wishbone Master)
wb_dma_rst_n_i : in std_logic; -- Active low reset in sync with wb_dma_clk_i
wb_dma_clk_i : in std_logic; -- Bus clock
wb_dma_i : in t_wishbone_master_in;
wb_dma_o : out t_wishbone_master_out;
---------------------------------------------------------
-- To the DMA controller
......@@ -113,12 +114,17 @@ entity p2l_dma_master is
end p2l_dma_master;
architecture behaviour of p2l_dma_master is
architecture arch of p2l_dma_master is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
-- Used to tweak the almost full flag threshold of the SYNC FIFO
-- in order to help with timing by giving an advanced warning
-- that we can then pipeline through an equal number of registers.
constant c_SYNC_FIFO_FULL_DELAY : natural := 3;
-- c_MAX_READ_REQ_SIZE is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_MAX_READ_REQ_SIZE values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
......@@ -163,7 +169,6 @@ architecture behaviour of p2l_dma_master is
signal to_wb_fifo_din : std_logic_vector(63 downto 0) := (others => '0');
signal to_wb_fifo_din_d : std_logic_vector(63 downto 0) := (others => '0');
signal to_wb_fifo_dout : std_logic_vector(63 downto 0);
signal to_wb_fifo_valid : std_logic;
signal to_wb_fifo_byte_swap : std_logic_vector(1 downto 0) := (others => '0');
-- wishbone
......@@ -192,20 +197,6 @@ architecture behaviour of p2l_dma_master is
begin
------------------------------------------------------------------------------
-- Active low reset for fifos
------------------------------------------------------------------------------
fifo_rst_n <= rst_n_i;
-- Local resynced copy of fifo_rst_n to make sure that both sides of the fifo
-- are reset if rst_n_i = '0'
cmp_wb_fifo_rst_sync: gc_sync_ffs
port map (
clk_i => p2l_dma_clk_i,
rst_n_i => p2l_dma_rst_n_i,
data_i => fifo_rst_n,
synced_o => wb_fifo_rst_n);
-- Errors to DMA controller
dma_ctrl_error_o <= dma_busy_error or completion_error;
......@@ -409,10 +400,10 @@ begin
-- NOTE: this pipeline was here before the reset and resync rehaul,
-- however it was clocked by the wrong clock (clk_i).
p_dma_stall_d2 : process (p2l_dma_clk_i)
p_dma_stall_d2 : process (wb_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
p2l_dma_stall_d(0) <= p2l_dma_stall_i;
if rising_edge(wb_dma_clk_i) then
p2l_dma_stall_d(0) <= wb_dma_i.stall;
p2l_dma_stall_d(1) <= p2l_dma_stall_d(0);
end if;
end process p_dma_stall_d2;
......@@ -519,51 +510,89 @@ begin
end process p_addr_cnt;
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
-- FIFO for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
------------------------------------------------------------------------------
cmp_to_wb_fifo : generic_async_fifo_dual_rst
generic map (
g_data_width => 64,
g_size => g_FIFO_SIZE,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => g_FIFO_FULL_THRES)
port map (
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din_d,
we_i => to_wb_fifo_wr_d,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
rst_rd_n_i => wb_fifo_rst_n,
clk_rd_i => p2l_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_fifo_valid : process(p2l_dma_clk_i)
-- Active low reset for fifos
------------------------------------------------------------------------------
fifo_rst_n <= rst_n_i;
gen_sync_fifo : if g_DMA_USE_PCI_CLK = TRUE generate
begin
if rising_edge(p2l_dma_clk_i) then
to_wb_fifo_valid <= to_wb_fifo_rd and (not to_wb_fifo_empty);
end if;
end process;
wb_fifo_rst_n <= fifo_rst_n;
cmp_to_wb_fifo : generic_sync_fifo
generic map (
g_DATA_WIDTH => 64,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_COUNT => FALSE)
port map (
rst_n_i => fifo_rst_n,
clk_i => clk_i,
-- write port
d_i => to_wb_fifo_din_d,
we_i => to_wb_fifo_wr_d,
full_o => to_wb_fifo_full,
-- read port
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
empty_o => to_wb_fifo_empty);
end generate gen_sync_fifo;
gen_async_fifo : if g_DMA_USE_PCI_CLK = FALSE generate
signal to_wb_fifo_full_d : std_logic_vector(c_SYNC_FIFO_FULL_DELAY - 1 downto 0) := (others => '0');
signal to_wb_fifo_full_next : std_logic;
begin
-- Local resynced copy of fifo_rst_n to make sure that both sides of the fifo
-- are reset if rst_n_i = '0'
cmp_wb_fifo_rst_sync : gc_sync
port map (
clk_i => wb_dma_clk_i,
rst_n_a_i => wb_dma_rst_n_i,
d_i => fifo_rst_n,
q_o => wb_fifo_rst_n);
-- Pipeline to_wb_fifo_full to help with timing. This requires the
-- equivalent setting in g_ALMOST_FULL_THRESHOLD to prevent overflows.
p_fifo_full_delay_reg : process (wb_dma_clk_i) is
begin
if rising_edge(wb_dma_clk_i) then
-- we want proper registers to help with timing and
-- having a reset prevents inferring of shift register.
if wb_fifo_rst_n = '0' then
to_wb_fifo_full_d <= (others => '0');
else
to_wb_fifo_full_d <= to_wb_fifo_full_d(to_wb_fifo_full_d'high-1 downto 0) & to_wb_fifo_full_next;
end if;
end if;
end process p_fifo_full_delay_reg;
to_wb_fifo_full <= to_wb_fifo_full_d(to_wb_fifo_full_d'high);
cmp_to_wb_fifo : generic_async_fifo_dual_rst
generic map (
g_DATA_WIDTH => 64,
g_SIZE => g_FIFO_SIZE,
g_SHOW_AHEAD => TRUE,
g_WITH_WR_FULL => FALSE,
g_WITH_WR_ALMOST_FULL => TRUE,
-- 20 less to give time to the GN4124 to react to P2L_RDY going low.
g_ALMOST_FULL_THRESHOLD => g_FIFO_SIZE - c_SYNC_FIFO_FULL_DELAY - 20)
port map (
-- write port
rst_wr_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din_d,
we_i => to_wb_fifo_wr_d,
wr_almost_full_o => to_wb_fifo_full_next,
-- read port
rst_rd_n_i => wb_fifo_rst_n,
clk_rd_i => wb_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty);
end generate gen_async_fifo;
-- pause transfer from GN4124 if fifo is (almost) full
p2l_rdy_o <= not(to_wb_fifo_full);
......@@ -574,27 +603,27 @@ begin
-- fifo read
to_wb_fifo_rd <= not(to_wb_fifo_empty)
and not(p2l_dma_stall_i);
and not(wb_dma_i.stall);
-- write only
p2l_dma_we_o <= '1';
wb_dma_o.we <= '1';
-- Wishbone master process
p_wb_master : process (p2l_dma_clk_i)
p_wb_master : process (wb_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
if rising_edge(wb_dma_clk_i) then
if wb_fifo_rst_n = '0' then
p2l_dma_cyc_t <= '0';
p2l_dma_stb_t <= '0';
else
-- data and address
if (to_wb_fifo_valid = '1') then
if (to_wb_fifo_rd = '1') then
p2l_dma_adr_t(31 downto 30) <= "00";
p2l_dma_adr_t(29 downto 0) <= to_wb_fifo_dout(61 downto 32);
p2l_dma_dat_t <= to_wb_fifo_dout(31 downto 0);
end if;
-- stb and sel signals management
if (to_wb_fifo_valid = '1') then
if (to_wb_fifo_empty = '0') then
p2l_dma_stb_t <= '1';
p2l_dma_sel_t <= (others => '1');
else
......@@ -602,7 +631,7 @@ begin
p2l_dma_sel_t <= (others => '0');
end if;
-- cyc signal management
if (to_wb_fifo_valid = '1') then
if (to_wb_fifo_rd = '1') then
p2l_dma_cyc_t <= '1';
elsif (wb_ack_cnt >= wb_write_cnt and p2l_dma_stall_d(1) = '0') then
-- last ack received -> end of the transaction
......@@ -613,20 +642,20 @@ begin
end process p_wb_master;
-- for read back
p2l_dma_cyc_o <= p2l_dma_cyc_t;
p2l_dma_stb_o <= p2l_dma_stb_t;
p2l_dma_sel_o <= p2l_dma_sel_t;
p2l_dma_adr_o <= p2l_dma_adr_t;
p2l_dma_dat_o <= p2l_dma_dat_t;
wb_dma_o.cyc <= p2l_dma_cyc_t;
wb_dma_o.stb <= p2l_dma_stb_t;
wb_dma_o.sel <= p2l_dma_sel_t;
wb_dma_o.adr <= p2l_dma_adr_t;
wb_dma_o.dat <= p2l_dma_dat_t;
-- Wishbone write cycle counter
p_wb_write_cnt : process (p2l_dma_clk_i)
p_wb_write_cnt : process (wb_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
if rising_edge(wb_dma_clk_i) then
if wb_fifo_rst_n = '0' then
wb_write_cnt <= (others => '0');
else
if (to_wb_fifo_valid = '1') then
if (to_wb_fifo_rd = '1') then
wb_write_cnt <= wb_write_cnt + 1;
end if;
end if;
......@@ -634,17 +663,17 @@ begin
end process p_wb_write_cnt;
-- Wishbone ack counter
p_wb_ack_cnt : process (p2l_dma_clk_i)
p_wb_ack_cnt : process (wb_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
if rising_edge(wb_dma_clk_i) then
if wb_fifo_rst_n = '0' then
wb_ack_cnt <= (others => '0');
else
if (p2l_dma_ack_i = '1' and p2l_dma_cyc_t = '1') then
if (wb_dma_i.ack = '1' and p2l_dma_cyc_t = '1') then
wb_ack_cnt <= wb_ack_cnt + 1;
end if;
end if;
end if;
end process p_wb_ack_cnt;
end behaviour;
end architecture arch;
hdl/rtl/spartan6/gn4124_core.vhd
View file @ 0284a69b
......@@ -52,9 +52,8 @@ entity gn4124_core is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_DATA_FIFO_SIZE : positive := 128;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
-- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT : positive := 100);
port (
......@@ -289,19 +288,6 @@ architecture rtl of gn4124_core is
signal dma_irq : std_logic;
attribute keep of dma_ctrl_l2p_error : signal is "TRUE";
attribute keep of dma_ctrl_l2p_done : signal is "TRUE";
attribute keep of dma_ctrl_start_l2p : signal is "TRUE";
attribute keep of dma_ctrl_abort : signal is "TRUE";
attribute keep of ldm_arb_valid : signal is "TRUE";
attribute keep of ldm_arb_dframe : signal is "TRUE";
attribute keep of ldm_arb_data : signal is "TRUE";
attribute keep of ldm_arb_req : signal is "TRUE";
attribute keep of l2p_rdy : signal is "TRUE";
attribute keep of l_wr_rdy : signal is "TRUE";
attribute keep of tx_error : signal is "TRUE";
attribute keep of arb_ldm_gnt : signal is "TRUE";
------------------------------------------------------------------------------
-- CSR wishbone bus
------------------------------------------------------------------------------
......@@ -313,14 +299,8 @@ architecture rtl of gn4124_core is
signal l2p_dma_in : t_wishbone_master_in;
signal l2p_dma_out : t_wishbone_master_out;
signal p2l_dma_adr : std_logic_vector(31 downto 0);
signal p2l_dma_dat : std_logic_vector(31 downto 0);
signal p2l_dma_sel : std_logic_vector(3 downto 0);
signal p2l_dma_cyc : std_logic;
signal p2l_dma_stb : std_logic;
signal p2l_dma_we : std_logic;
signal p2l_dma_ack : std_logic;
signal p2l_dma_stall : std_logic;
signal p2l_dma_in : t_wishbone_master_in;
signal p2l_dma_out : t_wishbone_master_out;
--==============================================================================
-- Architecture begin (gn4124_core)
......@@ -619,7 +599,7 @@ begin
cmp_l2p_dma_master : entity work.l2p_dma_master
generic map (
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_DATA_FIFO_SIZE => g_L2P_DATA_FIFO_SIZE,
g_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
port map (
clk_i => sys_clk,
......@@ -660,10 +640,9 @@ begin
-----------------------------------------------------------------------------
cmp_p2l_dma_master : entity work.p2l_dma_master
generic map (
--g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES,
g_BYTE_SWAP => TRUE)
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
port map (
clk_i => sys_clk,
rst_n_i => sys_rst_n,
......@@ -699,17 +678,10 @@ begin
pdm_arb_req_o => pdm_arb_req,
arb_pdm_gnt_i => arb_pdm_gnt,
p2l_dma_rst_n_i => dma_rst_n_i,
p2l_dma_clk_i => dma_clk_i,
p2l_dma_adr_o => p2l_dma_adr,
p2l_dma_dat_i => dma_dat_i,
p2l_dma_dat_o => p2l_dma_dat,
p2l_dma_sel_o => p2l_dma_sel,
p2l_dma_cyc_o => p2l_dma_cyc,
p2l_dma_stb_o => p2l_dma_stb,
p2l_dma_we_o => p2l_dma_we,
p2l_dma_ack_i => p2l_dma_ack,
p2l_dma_stall_i => p2l_dma_stall,
wb_dma_rst_n_i => wb_dma_rst_n,
wb_dma_clk_i => wb_dma_clk,
wb_dma_i => p2l_dma_in,
wb_dma_o => p2l_dma_out,
next_item_carrier_addr_o => next_item_carrier_addr,
next_item_host_addr_h_o => next_item_host_addr_h,
......@@ -721,9 +693,12 @@ begin
next_item_valid_o => next_item_valid
);
p2l_dma_in.dat <= dma_dat_i;
p2l_dma_in.err <= dma_err_i;
p2l_dma_in.rty <= dma_rty_i;
p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i,
l2p_dma_out, p2l_dma_adr, p2l_dma_cyc, p2l_dma_dat,
p2l_dma_sel, p2l_dma_stb, p2l_dma_we)
l2p_dma_out, p2l_dma_out)
begin
if (dma_ctrl_direction = '0') then
dma_adr_o <= l2p_dma_out.adr;
......@@ -734,17 +709,17 @@ begin
dma_we_o <= l2p_dma_out.we;
l2p_dma_in.ack <= dma_ack_i;
l2p_dma_in.stall <= dma_stall_i;
p2l_dma_ack <= '0';
p2l_dma_stall <= '0';
p2l_dma_in.ack <= '0';
p2l_dma_in.stall <= '0';
else
dma_adr_o <= p2l_dma_adr;
dma_dat_o <= p2l_dma_dat;
dma_sel_o <= p2l_dma_sel;
dma_cyc_o <= p2l_dma_cyc;
dma_stb_o <= p2l_dma_stb;
dma_we_o <= p2l_dma_we;
p2l_dma_ack <= dma_ack_i;
p2l_dma_stall <= dma_stall_i;
dma_adr_o <= p2l_dma_out.adr;
dma_dat_o <= p2l_dma_out.dat;
dma_sel_o <= p2l_dma_out.sel;
dma_cyc_o <= p2l_dma_out.cyc;
dma_stb_o <= p2l_dma_out.stb;
dma_we_o <= p2l_dma_out.we;
p2l_dma_in.ack <= dma_ack_i;
p2l_dma_in.stall <= dma_stall_i;
l2p_dma_in.ack <= '0';
l2p_dma_in.stall <= '0';
end if;
......
hdl/rtl/spartan6/gn4124_core_pkg.vhd
View file @ 0284a69b
......@@ -61,9 +61,8 @@ package gn4124_core_pkg is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_DATA_FIFO_SIZE : positive := 128;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
......@@ -122,9 +121,8 @@ package gn4124_core_pkg is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_DATA_FIFO_SIZE : positive := 128;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
g_ACK_TIMEOUT : positive := 100);
port (
---------------------------------------------------------
......
hdl/rtl/spartan6/xwb_gn4124_core.vhd
View file @ 0284a69b
......@@ -45,9 +45,8 @@ entity xwb_gn4124_core is
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_DATA_FIFO_SIZE : positive := 128;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
-- WB config for three WB interfaces
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
......@@ -204,8 +203,7 @@ begin
g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE,
g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES,
g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_P2L_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES,
g_L2P_DATA_FIFO_SIZE => g_L2P_DATA_FIFO_SIZE,
g_L2P_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_ACK_TIMEOUT => g_ACK_TIMEOUT)
port map (
rst_n_a_i => rst_n_a_i,
......
hdl/sim/example_tb/main.sv
View file @ 0284a69b
......@@ -54,13 +54,13 @@ module main;
logic wb_dma_clk;
logic wb_dma_rst_n;
initial begin
rst_125m_n = 0;
rst_62m5_n = 0;
rst_62m5_n = 0;
#80ns;
rst_125m_n = 1;
rst_62m5_n = 1;
rst_62m5_n = 1;
end
IGN4124PCIMaster i_gn4124 ();
......@@ -71,8 +71,8 @@ module main;
)
DUT (
.rst_n_a_i (i_gn4124.rst_n),
.clk_200m_o (clk_gn4124),
.rst_200m_n_o (rst_gn4124_n),
.clk_200m_o (clk_gn4124),
.rst_200m_n_o (rst_gn4124_n),
.p2l_clk_p_i (i_gn4124.p2l_clk_p),
.p2l_clk_n_i (i_gn4124.p2l_clk_n),
.p2l_data_i (i_gn4124.p2l_data),
......@@ -114,16 +114,17 @@ module main;
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_gn4124;
assign wb_dma_rst_n = rst_gn4124_n;
-----/\----- EXCLUDED -----/\----- */
assign wb_dma_clk = clk_125m;
assign wb_dma_rst_n = rst_125m_n;
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_62m5;
assign wb_dma_rst_n = rst_62m5_n;
-----/\----- EXCLUDED -----/\----- */
xwb_dpram #
(
.g_size (32),
.g_init_file ("mem_init.bram"),
.g_size (16384),
.g_slave1_interface_mode (1), // 1 = PIPELINED
.g_slave2_interface_mode (1),
.g_slave1_granularity (1), // 1 = WORD
......@@ -179,7 +180,7 @@ module main;
initial begin
automatic int ntest = 1;
const int tests = 9;
const int tests = 11;
uint32_t addr, val, expected;
......@@ -191,6 +192,7 @@ module main;
@(posedge clk_125m);
// ---------------------------------
$write("Test %0d/%0d: simple read/write accesses over Wishbone: ",
ntest++, tests);
......@@ -209,9 +211,11 @@ module main;
acc.write(addr, 'h0);
end
repeat(2) @(posedge clk_125m);
$write("PASS\n");
/* -----\/----- EXCLUDED -----\/-----
// ---------------------------------
$write("Test %0d/%0d: 128B read over DMA, abort after first read: ",
ntest++, tests);
......@@ -221,15 +225,8 @@ module main;
acc.write('h14, 'h80); // count
acc.write('h00, 'h01); // start
// Check values read from memory
@(posedge i_gn4124.l2p_valid); // skip header
repeat(2) @(posedge i_gn4124.l2p_clk_p);
expected = 32'h8000001f;
val = i_gn4124.l2p_data;
@(posedge i_gn4124.l2p_clk_n);
val |= i_gn4124.l2p_data << 16;
val_check("DMA read-back", 'h20, val, expected);
// wait for transfer to start
@(posedge i_gn4124.l2p_valid);
repeat(2) @(posedge clk_125m);
......@@ -241,14 +238,42 @@ module main;
repeat(2) @(posedge clk_125m);
$write("PASS\n");
-----/\----- EXCLUDED -----/\----- */
$write("Test %0d/%0d: 2x128B chained reads over DMA: ",
// ---------------------------------
$write("Test %0d/%0d: 256B DMA write: ",
ntest++, tests);
// Setup data in BFM memory
for (addr = 'h00; addr < 'h40; addr += 1)
i_gn4124.host_mem_write(4 * addr, 32'h80000020 - addr);
// Setup DMA
acc.write('h14, 'h100); // count
acc.write('h20, 'h01); // attrib
acc.write('h0c, 'h20000000); // hstartL
acc.write('h10, 'h00000000); // hstartH
acc.write('h00, 'h01); // start
@(posedge dma_irq);
check_irq_status;
clear_irq;
repeat(4) @(posedge clk_125m);
$write("PASS\n");
// wait for WB transfer to finish
#5us;
// ---------------------------------
$write("Test %0d/%0d: 2x128B chained DMA reads: ",
ntest++, tests);
// Setup DMA chain info in BFM memory
i_gn4124.host_mem_write('h20000, 'h00001000); // remote address
i_gn4124.host_mem_write('h20004, 'h20000100); // hstartL
i_gn4124.host_mem_write('h20000, 'h00000080); // remote address
i_gn4124.host_mem_write('h20004, 'h20000080); // hstartL
i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH
i_gn4124.host_mem_write('h2000C, 'h80); // count
i_gn4124.host_mem_write('h20010, 'h00); // nextL
......@@ -271,11 +296,10 @@ module main;
check_irq_status;
clear_irq;
for (addr = 'h00; addr < 'h20; addr += 1)
for (addr = 'h00; addr < 'h40; addr += 1)
begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
expected = 32'h80000020 - addr;
mem_check(4 * addr, expected);
mem_check('h100 + 4 * addr, expected);
end
repeat(4) @(posedge clk_125m);
......@@ -283,7 +307,7 @@ module main;
$write("PASS\n");
// ---------------------------------
$write("Test %0d/%0d: 256B read over DMA: ",
$write("Test %0d/%0d: 256B DMA read: ",
ntest++, tests);
// Setup DMA
......@@ -301,7 +325,7 @@ module main;
for (addr = 'h00; addr < 'h40; addr += 1)
begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
expected = 32'h80000020 - addr;
mem_check(4 * addr, expected);
end
......@@ -309,16 +333,57 @@ module main;
$write("PASS\n");
// ---------------------------------
$write("Test %0d/%0d: 2x4KiB chained DMA write: ",
ntest++, tests);
// Setup data in BFM memory
for (addr = 'h00; addr < 'h800; addr += 1)
i_gn4124.host_mem_write(4 * addr, 32'h80000020 - addr);
// Setup DMA chain info in BFM memory
i_gn4124.host_mem_write('h20000, 'h00001000); // remote address
i_gn4124.host_mem_write('h20004, 'h20001000); // hstartL
i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH
i_gn4124.host_mem_write('h2000C, 'h1000); // count
i_gn4124.host_mem_write('h20010, 'h00); // nextL
i_gn4124.host_mem_write('h20014, 'h00); // nextH
i_gn4124.host_mem_write('h20018, 'h01); // attrib
// Setup DMA
acc.write('h14, 'h1000); // count
acc.write('h20, 'h03); // attrib
acc.write('h0c, 'h20000000); // hstartL
acc.write('h10, 'h00000000); // hstartH
// Point to chain info in BFM memory
acc.write('h18, 'h20020000); // nextL
acc.write('h1C, 'h00000000); // nextH
acc.write('h00, 'h01); // start
@(posedge dma_irq);
check_irq_status;
clear_irq;
repeat(4) @(posedge clk_125m);
$write("PASS\n");
// wait for WB transfer to finish
#5us;
// Check all four byte swap settings
// ---------------------------------
for (int i = 0; i < 4; i++) begin
$write("Test %0d/%0d: 16KB read over DMA (byte swap = %0d): ",
$write("Test %0d/%0d: 8KiB DMA read (byte swap = %0d): ",
ntest++, tests, i);
// Restart
acc.write('h14, 'h4000); // count
acc.write('h14, 'h2000); // count
acc.write('h20, 'h00); // attrib
acc.write('h0c, 'h20000000 + i * 'h4000); // hstartL
acc.write('h0c, 'h20000000); // hstartL
acc.write('h10, 'h00000000); // hstartH
acc.write('h00, (i << 2) | 'h01); // start
......@@ -326,16 +391,16 @@ module main;
check_irq_status;
for (addr = 'h00; addr < 'h1000; addr += 1)
for (addr = 'h00; addr < 'h800; addr += 1)
begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
expected = 32'h80000020 - addr;
if (i == 1)
expected = {<<8{expected}};
else if (i == 2)
expected = {<<16{expected}};
else if (i == 3)
expected = {<<16{{<<8{expected}}}};
mem_check((i * 'h4000) + 4 * addr, expected);
mem_check(4 * addr, expected);
end
clear_irq;
......@@ -347,26 +412,26 @@ module main;
#1us;
end
$write("Test %0d/%0d: 8KB read over DMA with 32bit host address overflow: ",
$write("Test %0d/%0d: 256B DMA read with 32bit host address overflow: ",
ntest++, tests);
acc.write('h14, 'h2000); // count
acc.write('h14, 'h100); // count
acc.write('h20, 'h00); // attrib
acc.write('h0c, 'hfffff000); // hstartL
acc.write('h0c, 'hffffff80); // hstartL
acc.write('h10, 'h00000000); // hstartH
acc.write('h00, 'h01); // start
// Transfer will be split internally by L2P DMA master in two requests, the first
// one with a 32-bit adress starting at ffff_f000 and the next one with a 64-bit
// one with a 32-bit adress starting at ffff_ff80 and the next one with a 64-bit
// address starting at 1_0000_0000
@(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow header", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h02ff0000);
val_check("Host address overflow header", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h02ff0020);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow address", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'hfffff000);
val_check("Host address overflow address", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'hffffff80);
@(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow header", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h03ff0000);
val_check("Host address overflow header", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h03ff0020);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow address high", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 1);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk);
......
hdl/sim/example_tb/mem_init.bram deleted 100644 → 0
View file @ f1e9a982
10000000000000000000000000011111
10000000000000000000000000011110
10000000000000000000000000011101
10000000000000000000000000011100
10000000000000000000000000011011
10000000000000000000000000011010
10000000000000000000000000011001
10000000000000000000000000011000
10000000000000000000000000010111
10000000000000000000000000010110
10000000000000000000000000010101
10000000000000000000000000010100
10000000000000000000000000010011
10000000000000000000000000010010
10000000000000000000000000010001
10000000000000000000000000010000
10000000000000000000000000001111
10000000000000000000000000001110
10000000000000000000000000001101
10000000000000000000000000001100
10000000000000000000000000001011
10000000000000000000000000001010
10000000000000000000000000001001
10000000000000000000000000001000
10000000000000000000000000000111
10000000000000000000000000000110
10000000000000000000000000000101
10000000000000000000000000000100
10000000000000000000000000000011
10000000000000000000000000000010
10000000000000000000000000000001
10000000000000000000000000000000
hdl/sim/example_tb/wave.do
View file @ 0284a69b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate -expand -group L2P /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_dout
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/dma_packet_len
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate -expand -group L2P -color Magenta /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/clk_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/target_addr_cnt
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/pd_pdm_data_valid_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/pd_pdm_data_i
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_wr_d
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_din_d
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_full
add wave -noupdate -expand -group P2L -color {Indian Red} /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/p2l_rdy_o
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_clk_i
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_empty
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_rd
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_dout
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/to_wb_fifo_valid
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_o
add wave -noupdate -expand -group P2L /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_p2l_dma_master/wb_dma_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_clk_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_cyc_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_stb_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_we_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_ack_o
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_adr_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_i
add wave -noupdate -expand -group {DMA Controller} -color Thistle /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_abort_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_error_i
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_done_i
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_irq_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_direction_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_carrier_addr_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_h_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_l_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_len_o
add wave -noupdate -expand -group {DMA Controller} -color Cyan /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {537831000 ps} 0}
WaveRestoreCursors {{Cursor 1} {6339711 ps} 0} {{Cursor 2} {129899342 ps} 1}
quietly wave cursor active 1
configure wave -namecolwidth 199
configure wave -valuecolwidth 100
configure wave -namecolwidth 277
configure wave -valuecolwidth 210
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
......@@ -31,4 +72,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {737045400 ps}
WaveRestoreZoom {0 ps} {24072512 ps}
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