Important changes include:

1. Clear separation of resets per clock domain (with the exception
   of the wbgen-generated dma controller registers).

2. Conversion of all processes to use synchronous resets when the
   reset is synced with the clock of the process.

3. Use of standard synchronizers from general-cores when crossing
   clock-domains.

Due to the change in processes to use sync resets, a lot of code
has changed indentation. To this end, it might be useful to perform
a case insensitive diff when studying the changes of this commit.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Fake merge (using 'ours' strategy) to make sure that commit 2710742b stays, since it is used by a BTrain-over-WR release.

The commit itself is already rebased onto proposed_master as 9b9625bb.

sim: SV BFM assignment to port does not need MODPORT, greatly reduces number of warnings in Modelsim

rtl/wbmaster32: fix a nasty freeze when accesses are very tightly spaced: CIDs should be also FIFOed!

The sizes of to_wb and from_wb fifo were reduced in commit 4a430afa from 512 to
128 words. However, almost_full thresholds were still set to 500. As the
result some of the requests were lost when fifo was full because this fact was
never signaled to the gn4124 chip.