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Platform-independent core collection
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Platform-independent core collection
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43
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18
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66
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2 new WB cores
!26
· opened
Dec 15, 2022
by
Tomasz Wlostowski
proposed_master
MERGED
4
updated
Dec 16, 2022
Genrams improvements
!25
· opened
Dec 15, 2022
by
Tomasz Wlostowski
proposed_master
MERGED
2
updated
Dec 16, 2022
DSP core collection
!24
· opened
Dec 15, 2022
by
Tomasz Wlostowski
proposed_master
CLOSED
3
updated
May 08, 2023
Minor updates to the AXI4 package
!23
· opened
Dec 15, 2022
by
Tomasz Wlostowski
proposed_master
3
updated
Dec 16, 2022
Rework of SystemVerilog shared simulation code
!22
· opened
Dec 15, 2022
by
Tomasz Wlostowski
proposed_master
5
updated
Dec 16, 2022
Resolve "tools: generate version information in gen_sourceid.py"
!21
· opened
Dec 15, 2022
by
Dimitris Lampridis
MERGED
2
updated
Dec 15, 2022
Wb axi4lite bridge fix
!20
· opened
Oct 09, 2022
by
Peter Jansweijer
CLOSED
1
updated
Oct 10, 2022
hdl/sim: Protect CIWBMasterAccessor against multiple requests
!19
· opened
Jul 14, 2022
by
Dimitris Lampridis
proposed_master
MERGED
17
updated
Jul 18, 2022
Making libs more versatile for Altera/Modelsim
!18
· opened
Jun 27, 2022
by
David Belohrad
proposed_master
CLOSED
1
updated
Jun 28, 2022
Fixed an issue where the "RESPONSE_READ" was skipped.
!17
· opened
May 13, 2022
by
Pascal Bos
proposed_master
bug
0
updated
May 13, 2022
Add scoped XDC constraints for CDC modules
!16
· opened
Sep 30, 2021
by
Adrian Byszuk
proposed_master
MERGED
1
updated
Oct 01, 2021
Fix reset CDC issue in gc_sync_word_rd
!15
· opened
Sep 28, 2021
by
Adrian Byszuk
proposed_master
MERGED
1
updated
Sep 29, 2021
Fix wb_ack_o violation in wb_simple_timer
!14
· opened
Sep 28, 2021
by
Adrian Byszuk
proposed_master
MERGED
1
updated
Sep 29, 2021
Condition check for Divider value
!13
· opened
Oct 22, 2020
by
Mamta Shukla
CLOSED
1
updated
Oct 22, 2020
Merge current master into current GSI development branch
!12
· opened
Oct 12, 2020
by
A. Hahn
gsi_master_get_back_on_track_aug_2020
CLOSED
0
updated
Oct 12, 2020
Fixes to the latest proposed_master merge
!11
· opened
Sep 15, 2020
by
Grzegorz Daniluk
proposed_master
MERGED
0
updated
Sep 17, 2020
[sw][driver][spi]: Update actual_length to fix I/O error
!10
· opened
Sep 11, 2020
by
Mamta Shukla
CLOSED
1
updated
Sep 14, 2020
AFCZ-related fixes (SPI, etc)
!9
· opened
Aug 27, 2020
by
Tomasz Wlostowski
proposed_master
CLOSED
1
updated
Sep 09, 2020
Fine Pulse Generator for sis83k/eRTM
!8
· opened
Aug 27, 2020
by
Tomasz Wlostowski
proposed_master
CLOSED
1
updated
Sep 09, 2020
Fixes in AXI4Lite to WB bridge
!7
· opened
Apr 30, 2020
by
Olof Kindgren
proposed_master
CLOSED
2
updated
Sep 09, 2020
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