Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
P
Platform-independent core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
18
Issues
18
List
Board
Labels
Milestones
Merge Requests
5
Merge Requests
5
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Platform-independent core collection
Merge Requests
Open
5
Merged
40
Closed
18
All
63
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Popularity
Label priority
Resolve "Support Verilog output with gen_sourceid tool"
!63
· opened
Jan 30, 2024
by
Dimitris Lampridis
MERGED
1
updated
Jan 30, 2024
Resolve "Linux driver for wb simple uart"
!62
· opened
Jan 24, 2024
by
Konstantinos Blantos
software
MERGED
0
updated
Mar 11, 2024
Resolve "possible_fix_in_wb_uart_rx_fifo"
!61
· opened
Jan 23, 2024
by
Konstantinos Blantos
CLOSED
0
updated
Jan 26, 2024
Create branch wb_axi_bridge_fix and add fix for wb - axi4 lite bridge
!60
· opened
Jan 23, 2024
by
Quentin Genoud
MERGED
0
updated
Jan 23, 2024
WIP: Resolve "inferred_async_fifo_dual_reset : spurious pulse on almost_full_int after reset"
!59
· opened
Jan 22, 2024
by
Alexis Marquet
0
updated
Jan 22, 2024
Resolve "add rx/tx interrupt enable in wb_uart"
!58
· opened
Jan 15, 2024
by
Konstantinos Blantos
MERGED
4
updated
Jan 26, 2024
Resolve "add a fifo with mixed width"
!57
· opened
Dec 21, 2023
by
Tristan Gingold
MERGED
1
updated
Jan 26, 2024
Resolve "fifo: minor cleanup"
!56
· opened
Dec 20, 2023
by
Tristan Gingold
MERGED
0
updated
Dec 20, 2023
Resolve "demo_vunit_ghdl_testbench"
!55
· opened
Dec 12, 2023
by
Konstantinos Blantos
kostas_dev
4
updated
Feb 21, 2024
Resolve "Addition of a register in wb_uart to show the endianess"
!54
· opened
Dec 08, 2023
by
Konstantinos Blantos
CLOSED
0
updated
Jan 15, 2024
Addition of 2 bits in status register to clarify if you are using Virtual or Physical UART
!53
· opened
Dec 04, 2023
by
Konstantinos Blantos
MERGED
10
updated
Dec 08, 2023
WIP: Resolve "wb_uart new features"
!52
· opened
Dec 04, 2023
by
Konstantinos Blantos
CLOSED
1
updated
Dec 04, 2023
WIP: Resolve "wb_uart new features"
!51
· opened
Dec 04, 2023
by
Konstantinos Blantos
CLOSED
0
updated
Dec 04, 2023
update CHANGELOG sw changes
!50
· opened
Oct 18, 2023
by
Federico Vaga
MERGED
0
updated
Oct 18, 2023
mpsoc_int_gen: fix a dead-lock
!49
· opened
Oct 10, 2023
by
Tristan Gingold
proposed_master
MERGED
0
updated
Oct 10, 2023
modules/axi: add mpsoc_int_gen (to generate pcie interrupts)
!48
· opened
Oct 06, 2023
by
Tristan Gingold
proposed_master
MERGED
0
updated
Oct 06, 2023
modules/axi: add mpsoc_int_gen (to generate pcie interrupts)
!47
· opened
Oct 06, 2023
by
Tristan Gingold
MERGED
0
updated
Oct 06, 2023
fix: improve filtering to include prefixed sync_word and multi-aasd
!46
· opened
Sep 05, 2023
by
Alexis Marquet
MERGED
0
updated
Sep 18, 2023
fix: skip constraints gen for optimized out destination pins
!45
· opened
Sep 05, 2023
by
Alexis Marquet
MERGED
0
updated
Sep 05, 2023
tools: trying to improve the CDC primitive constraint scripts to find all…
!44
· opened
Sep 04, 2023
by
Tristan Gingold
MERGED
0
updated
Sep 04, 2023
Prev
1
2
3
4
Next