Programming languages used in this repository

  •   Verilog
    48.78 %
  •   VHDL
    45.04 %
  •   C
    2.5 %
  •   SystemVerilog
    1.0 %
  •   Python
    0.89 %
  •   Stata
    0.54 %
  •   Assembly
    0.46 %
  •   Lua
    0.37 %
  •   Tcl
    0.23 %
  •   Makefile
    0.15 %
  •   Shell
    0.02 %
  •   C++
    0.02 %

Commit statistics for master Apr 18 - Oct 21

  • Total: 779 commits
  • Average per day: 0.3 commits
  • Authors: 22

Commits per day of month

Commits per weekday

Commits per day hour (UTC)