update CHANGELOG sw changes

See merge request !50

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

modules/axi: add mpsoc_int_gen (to generate pcie interrupts)

See merge request !47

fix: improve filtering to include prefixed sync_word and multi-aasd

See merge request !46

fix: skip constraints gen for optimized out destination pins

See merge request !45

tools: trying to improve the CDC primitive constraint scripts to find all…

See merge request !44

tools: trying to improve the CDC primitive constraint scripts to find all GC_sync and constrain them correctly, wip

software/spi-ocores/drivers/spi/spi-ocores: fix build with kernel >= 5.13.0

See merge request !42

Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>

generate_cdc_constraints: handle gc_sync_word_*

See merge request !41

Fix some warnings

Resolve "fine_pulse_gen: tune clocking"

See merge request !40

Resolve "genram_pkg: disable bound checking in synthesis"

See merge request !39

Resolve "gc_serial_dac avoid overwrite"

See merge request !38

This fixes a bug causing the TX value to lose it's LSB when valid_i is asserted before the current transfer has finished.

Resolve "add keep attributes"

See merge request !37

gc_reset_multi_aasd: add KEEP property on rst_chains so that we can easily constrain their timing in XDC

Resolve "gc_pulse_synchronizer2 use async reset"

See merge request !36

Resolve "gc_sync (and other CDC constraints) not recognized by Vivado"

See merge request !35

Add DSP cores

See merge request !32

also define missing uint_8 type

dsp: don't use generics (even statically evaluable) in case statement, it's not fully VHDL-compliant. Kudos to Tristan!

dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.

dsp/gc_pi_regulator: synthesis fails when g_INTEGRATOR_BITS is bigger than 32 as the vhdl integer type is only 32 bits wide. Removing unused constants.