gc_sync[register]: keep attribute on the input clock pin [clk_i] for easy constraints

7139f6be · Tomasz Wlostowski · Tristan Gingold · fe61607c · 7139f6be · 7139f6be
Commit 7139f6be authored May 30, 2023 by Tomasz Wlostowski Committed by Tristan Gingold Jun 01, 2023
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gc_sync.vhd modules/common/gc_sync.vhd +1 -0

gc_sync_register.vhd modules/common/gc_sync_register.vhd +1 -0

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--- a/modules/common/gc_sync.vhd
+++ b/modules/common/gc_sync.vhd
@@ -57,6 +57,7 @@ architecture arch of gc_sync is
  attribute shreg_extract of sync1 : signal is "no";

  attribute keep                   : string;
+  attribute keep of clk_i          : signal is "true";
  attribute keep of gc_sync_ffs_in : signal is "true";
  attribute keep of sync0          : signal is "true";
  attribute keep of sync1          : signal is "true";

--- a/modules/common/gc_sync_register.vhd
+++ b/modules/common/gc_sync_register.vhd
@@ -50,6 +50,7 @@ architecture rtl of gc_sync_register is
  attribute shreg_extract of sync1               : signal is "no";

  attribute keep                        : string;
+  attribute keep of clk_i               : signal is "true";
  attribute keep of gc_sync_register_in : signal is "true";
  attribute keep of sync0               : signal is "true";
  attribute keep of sync1               : signal is "true";