The so-called "inferred_X_fifo" are basically generics fifos using
inferred rams blocks from altera or xilinx, depending the target
platform. That's why it makes more sense to move them to the "generic"
folder of genrams. This change forces to rename the "generic_X_fifo"
under "altera". Since these fifos are using the altera fifo  Megafunction,
are going to be called "altera_X_fifo". The Manifest has been changed accordingly.

PCIe must respond to reads within a fairly tight deadline.
If we allow too many enqueued operations, that deadline may be missed.
Using a smaller FIFO depth causes back-pressure on the PCIe bus, slowing the
request arrival rate and thus increasing the time a single WB op can take.

Concretely, this makes it possible to perform an SPI flash write within
the PCIe time limit.

If a Wishbone master lowers the cycle line before receiving its acks, it is
non-conforming.  However, it is probably a good idea to not let an honest
slave (whose ack then comes in outside of the cycle) be penalized for that
master's misbehaviour.

This small change ensures the FIFO does not leak space in this case.

There was a bug in the wb_i2c_bridge that manifested itself a WB slave of the
wb_i2c_master module replies by an error to the write command. The bridge FSM
was buggy and was not clearing the WB signals, which led to the next WB transfer
in the sequence (any access to the I2C slave) failing.

This error was fixed by clearing the WB signals on error as well and the slave
now replies properly.

The WB signals are properly cleared on WB error in the case of a read, so this
issue does not exist.

Sometimes a master needs to stop the flow of acks.

If you use a PLL locked signal for reset, synchronous reset does
not work. That's b/c the clock doesn't run while reset is asserted.

One shouldn't do that, but sometimes it is convenient when testing.

The simulator is crashing at the end of the LM32 startup code when it tries to
access the highest RAM location (at the stack pointer). After this access, the
LM32 verilog code already increments the address to be prepared for the next
cycle, which will never actually happen because you are at the end of the RAM.
It is this address increment in verilog that is one address outside the defined
RAM array for which the simulator complains and terminates. The actual
synthesized code is perfectly fine; no accesses outside RAM.

Tried in real hardware and this works better.

FIFO counters to other clock domain. Allows to constrain the maximum sync chain delay in a single UCF line.

gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;

Now wb_spi has generic parameters to configure registers length and number of
spi slaves. Reason for that is to keep default configuration in the repository
but also allow to adjust settings for WR Switch synthesis (and save resources).

The values used in WR Switch software fit in 8-bit registers so using 16-bits
in HDL was waste of resources.

Commit adds new WB register(IFS) that selects to which I2C interface master
should talk to. All other interfaces are then hold in idle state. IFS contains
also BUSY bit that is written only by host and marks that I2C Master is
currently in use and cannot be switched to another I2C interface. Host must
clear BUSY flag after the interaction with I2C interface is finished.

Even when g_num_pins was a small number, the registers inside were 32-bits, e.g. for g_num_pins=1 the module utilized 65 slice registers.

This is done to better reflect the interface of the module (structured Wishbone).
The documentation of the module is also changed in this respect.

If a very fast WB master queues a single-byte SPI command followed
immediately by the execute instruction, the SPI command will use
the old data in the FIFO. This delays execution by 1 cycle.