Commit bd7bca1c authored by Cesar Prados's avatar Cesar Prados

generic_fifos: reorganization of the inferred, generic and altera fifos

The so-called "inferred_X_fifo" are basically generics fifos using
inferred rams blocks from altera or xilinx, depending the target
platform. That's why it makes more sense to move them to the "generic"
folder of genrams. This change forces to rename the "generic_X_fifo"
under "altera". Since these fifos are using the altera fifo  Megafunction,
are going to be called "altera_X_fifo". The Manifest has been changed accordingly.
parent 2f134e41
files = [
"genram_pkg.vhd",
"memory_loader_pkg.vhd",
"generic_shiftreg_fifo.vhd",
"inferred_sync_fifo.vhd",
"inferred_async_fifo.vhd"];
"genram_pkg.vhd",
"memory_loader_pkg.vhd"];
if (target == "altera"):
modules = {"local" : "altera"}
modules = {"local" : ["altera", "generic"]}
elif (target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
modules = {"local" : ["xilinx", "xilinx/virtex6"]}
elif (target == "xilinx"):
......
files = [
"generic_async_fifo.vhd",
"altera_async_fifo.vhd",
"generic_simple_dpram.vhd",
"generic_dpram.vhd",
"generic_spram.vhd",
"generic_dpram_mixed.vhd",
"generic_sync_fifo.vhd",
"altera_sync_fifo.vhd",
"gc_shiftreg.vhd"]
......@@ -34,7 +34,7 @@ use altera_mf.all;
use work.genram_pkg.all;
entity generic_async_fifo is
entity altera_async_fifo is
generic (
g_data_width : natural;
......@@ -85,9 +85,9 @@ entity generic_async_fifo is
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_async_fifo;
end altera_async_fifo;
architecture syn of generic_async_fifo is
architecture syn of altera_async_fifo is
component dcfifo
generic (
......
......@@ -32,7 +32,7 @@ use altera_mf.all;
use work.genram_pkg.all;
entity generic_sync_fifo is
entity altera_sync_fifo is
generic (
g_data_width : natural;
......@@ -67,9 +67,9 @@ entity generic_sync_fifo is
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
end altera_sync_fifo;
architecture syn of generic_sync_fifo is
architecture syn of altera_sync_fifo is
component scfifo
generic (
......
files = ["generic_async_fifo.vhd",
"generic_sync_fifo.vhd"]
"generic_sync_fifo.vhd",
"inferred_sync_fifo.vhd",
"generic_shiftreg_fifo.vhd",
"inferred_async_fifo.vhd"]
......@@ -91,7 +91,7 @@ begin -- syn
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_addr_conflict_resolution => "dont_care",
g_dual_clock => false)
port map (
rst_n_i => rst_n_i,
......
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