Skip to content

P
Platform-independent core collection
Commit ef8a39f7 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana Committed by Tomasz Wlostowski
Browse files
Options

multiboot: Updated wbgen2 file for documentation 

Also updated the rest of the documentation file to have a pretty
regmap.
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent c63535f0
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 415 additions and 291 deletions
doc/wb_xil_multiboot/cern-title.tex
View file @ ef8a39f7
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm} \noindent \rule{\textwidth}{.1cm}
\hfill\today \hfill February 13, 2014
\vspace*{3cm} \vspace*{3cm}
......
doc/wb_xil_multiboot/multiboot-regs.tex 0 → 100644
View file @ ef8a39f7
\section{MultiBoot controller}
\label{app:memmap}
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x00000000 & CR & Control Register\\
0x4 & 0x00000000 & SR & Status Register\\
0x8 & 0x00000000 & GBBAR & Golden Bitstream Base Address Register\\
0xc & 0x00000000 & MBBAR & MultiBoot Bitstream Base Address Register\\
0x10 & 0x10000000 & FAR & Flash Access Register\\
\end{longtable}
}
\vspace{11pt}
\subsection{CR -- Control Register}
\label{app:memmap-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG\_UNLOCK}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RDCFGREG} & \multicolumn{6}{|c|}{\cellcolor{gray!25}CFGREGADR[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGADR
} [\emph{read/write}]: Configuration register address
\\
Address of FPGA configuration register to read.
\end{small}
\item \begin{small}
{\bf
RDCFGREG
} [\emph{write-only}]: Read FPGA configuration register
\\
1 -- Start FPGA configuration register sequence. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG\_UNLOCK
} [\emph{read/write}]: Unlock bit for the IPROG command
\\
1 -- Unlock IPROG bit. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG
} [\emph{read/write}]: Start IPROG sequence
\\
1 -- Start IPROG configuration sequence \\ 0 -- No effect \\ This bit needs to be unlocked by writing the IPROG\_UNLOCK bit first. \\ A write to this bit with IPROG\_UNLOCK cleared has no effect.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{SR -- Status Register}
\label{app:memmap-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IMGVALID}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGIMG
} [\emph{read-only}]: Configuration register image
\\
Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\cite{ug380}); validated by IMGVALID bit
\end{small}
\item \begin{small}
{\bf
IMGVALID
} [\emph{read-only}]: Configuration register image valid
\\
1 -- CFGREGIMG valid \\ 0 -- CFGREGIMG not valid;
\end{small}
\item \begin{small}
{\bf
WDTO
} [\emph{read/write}]: MultiBoot FSM stalled at one point and was reset by FSM watchdog
\\
1 -- FSM watchdog fired \\ 0 -- FSM watchdog has not fired
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:memmap-gbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of GBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- Golden bitstream address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:memmap-mbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of MBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- MultiBoot bitstream start address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{FAR -- Flash Access Register}
\label{app:memmap-far}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}READY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}XFER} & \multicolumn{2}{|c|}{\cellcolor{gray!25}NBYTES[1:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read/write}]: Flash data field
\\
23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \\ 15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \\ 7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash
\end{small}
\item \begin{small}
{\bf
NBYTES
} [\emph{read/write}]: Number of DATA fields to send and receive in one transfer:
\\
0x0 -- Send 1 byte (DATA[0]) \\ 0x1 -- Send 2 bytes (DATA[0], DATA[1]) \\ 0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])
\end{small}
\item \begin{small}
{\bf
XFER
} [\emph{write-only}]: Start transfer to and from flash
\\
1 -- Start transfer \\ 0 -- Idle
\end{small}
\item \begin{small}
{\bf
CS
} [\emph{read/write}]: Chip select bit
\\
1 - Flash chip selected (CS pin low) \\ 0 - Flash chip not selected (CS pin is high)
\end{small}
\item \begin{small}
{\bf
READY
} [\emph{read-only}]: Flash access ready
\\
1 - Flash access completed \\ 0 - Flash access in progress
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
doc/wb_xil_multiboot/wb_xil_multiboot.tex
View file @ ef8a39f7
This diff is collapsed.
platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
View file @ ef8a39f7
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for wb_xil_multiboot registers -- Title : Wishbone slave core for MultiBoot controller
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : multiboot_regs.vhd -- File : multiboot_regs.vhd
-- Author : auto-generated by wbgen2 from multiboot_regs.wb -- Author : auto-generated by wbgen2 from multiboot_regs.wb
-- Created : Fri Dec 6 15:51:10 2013 -- Created : Thu Feb 13 18:39:52 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE multiboot_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE multiboot_regs.wb
...@@ -27,41 +27,41 @@ entity multiboot_regs is ...@@ -27,41 +27,41 @@ entity multiboot_regs is
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'CFGREGADR' in reg: 'Control Register' -- Port for std_logic_vector field: 'Configuration register address' in reg: 'CR'
reg_cr_cfgregadr_o : out std_logic_vector(5 downto 0); reg_cr_cfgregadr_o : out std_logic_vector(5 downto 0);
-- Port for MONOSTABLE field: 'RDCFGREG' in reg: 'Control Register' -- Port for MONOSTABLE field: 'Read FPGA configuration register' in reg: 'CR'
reg_cr_rdcfgreg_o : out std_logic; reg_cr_rdcfgreg_o : out std_logic;
-- Ports for BIT field: 'IPROG_UNLOCK' in reg: 'Control Register' -- Ports for BIT field: 'Unlock bit for the IPROG command' in reg: 'CR'
reg_cr_iprog_unlock_o : out std_logic; reg_cr_iprog_unlock_o : out std_logic;
reg_cr_iprog_unlock_i : in std_logic; reg_cr_iprog_unlock_i : in std_logic;
reg_cr_iprog_unlock_load_o : out std_logic; reg_cr_iprog_unlock_load_o : out std_logic;
-- Ports for BIT field: 'IPROG' in reg: 'Control Register' -- Ports for BIT field: 'Start IPROG sequence' in reg: 'CR'
reg_cr_iprog_o : out std_logic; reg_cr_iprog_o : out std_logic;
reg_cr_iprog_i : in std_logic; reg_cr_iprog_i : in std_logic;
reg_cr_iprog_load_o : out std_logic; reg_cr_iprog_load_o : out std_logic;
-- Port for std_logic_vector field: 'CFGREGIMG' in reg: 'Status Register' -- Port for std_logic_vector field: 'Configuration register image' in reg: 'SR'
reg_sr_cfgregimg_i : in std_logic_vector(15 downto 0); reg_sr_cfgregimg_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'IMGVALID' in reg: 'Status Register' -- Port for BIT field: 'Configuration register image valid' in reg: 'SR'
reg_sr_imgvalid_i : in std_logic; reg_sr_imgvalid_i : in std_logic;
-- Ports for BIT field: 'WDTO' in reg: 'Status Register' -- Ports for BIT field: 'MultiBoot FSM stalled at one point and was reset by FSM watchdog' in reg: 'SR'
reg_sr_wdto_o : out std_logic; reg_sr_wdto_o : out std_logic;
reg_sr_wdto_i : in std_logic; reg_sr_wdto_i : in std_logic;
reg_sr_wdto_load_o : out std_logic; reg_sr_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'GBBAR' in reg: 'Golden Bitstream Base Address Register' -- Port for std_logic_vector field: 'Bits of GBBAR register' in reg: 'GBBAR'
reg_gbbar_bits_o : out std_logic_vector(31 downto 0); reg_gbbar_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MBBAR' in reg: 'MultiBoot Bitstream Base Address Register' -- Port for std_logic_vector field: 'Bits of MBBAR register' in reg: 'MBBAR'
reg_mbbar_bits_o : out std_logic_vector(31 downto 0); reg_mbbar_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'DATA' in reg: 'Flash Access Register' -- Port for std_logic_vector field: 'Flash data field' in reg: 'FAR'
reg_far_data_o : out std_logic_vector(23 downto 0); reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_data_i : in std_logic_vector(23 downto 0); reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_load_o : out std_logic; reg_far_data_load_o : out std_logic;
-- Port for std_logic_vector field: 'NBYTES' in reg: 'Flash Access Register' -- Port for std_logic_vector field: 'Number of DATA fields to send and receive in one transfer:' in reg: 'FAR'
reg_far_nbytes_o : out std_logic_vector(1 downto 0); reg_far_nbytes_o : out std_logic_vector(1 downto 0);
-- Port for MONOSTABLE field: 'XFER' in reg: 'Flash Access Register' -- Port for MONOSTABLE field: 'Start transfer to and from flash' in reg: 'FAR'
reg_far_xfer_o : out std_logic; reg_far_xfer_o : out std_logic;
-- Port for BIT field: 'CS' in reg: 'Flash Access Register' -- Port for BIT field: 'Chip select bit' in reg: 'FAR'
reg_far_cs_o : out std_logic; reg_far_cs_o : out std_logic;
-- Port for BIT field: 'READY' in reg: 'Flash Access Register' -- Port for BIT field: 'Flash access ready' in reg: 'FAR'
reg_far_ready_i : in std_logic reg_far_ready_i : in std_logic
); );
end multiboot_regs; end multiboot_regs;
...@@ -240,9 +240,9 @@ begin ...@@ -240,9 +240,9 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_dat_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- CFGREGADR -- Configuration register address
reg_cr_cfgregadr_o <= reg_cr_cfgregadr_int; reg_cr_cfgregadr_o <= reg_cr_cfgregadr_int;
-- RDCFGREG -- Read FPGA configuration register
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -255,23 +255,23 @@ begin ...@@ -255,23 +255,23 @@ begin
end process; end process;
-- IPROG_UNLOCK -- Unlock bit for the IPROG command
reg_cr_iprog_unlock_o <= wrdata_reg(16); reg_cr_iprog_unlock_o <= wrdata_reg(16);
-- IPROG -- Start IPROG sequence
reg_cr_iprog_o <= wrdata_reg(17); reg_cr_iprog_o <= wrdata_reg(17);
-- CFGREGIMG -- Configuration register image
-- IMGVALID -- Configuration register image valid
-- WDTO -- MultiBoot FSM stalled at one point and was reset by FSM watchdog
reg_sr_wdto_o <= wrdata_reg(17); reg_sr_wdto_o <= wrdata_reg(17);
-- GBBAR -- Bits of GBBAR register
reg_gbbar_bits_o <= reg_gbbar_bits_int; reg_gbbar_bits_o <= reg_gbbar_bits_int;
-- MBBAR -- Bits of MBBAR register
reg_mbbar_bits_o <= reg_mbbar_bits_int; reg_mbbar_bits_o <= reg_mbbar_bits_int;
-- DATA -- Flash data field
reg_far_data_o <= wrdata_reg(23 downto 0); reg_far_data_o <= wrdata_reg(23 downto 0);
-- NBYTES -- Number of DATA fields to send and receive in one transfer:
reg_far_nbytes_o <= reg_far_nbytes_int; reg_far_nbytes_o <= reg_far_nbytes_int;
-- XFER -- Start transfer to and from flash
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -284,9 +284,9 @@ begin ...@@ -284,9 +284,9 @@ begin
end process; end process;
-- CS -- Chip select bit
reg_far_cs_o <= reg_far_cs_int; reg_far_cs_o <= reg_far_cs_int;
-- READY -- Flash access ready
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
......
platform/xilinx/wb_xil_multiboot/multiboot_regs.wb
View file @ ef8a39f7
peripheral { peripheral {
name = "wb_xil_multiboot registers"; name = "MultiBoot controller";
hdl_entity = "multiboot_regs"; hdl_entity = "multiboot_regs";
prefix = "reg"; prefix = "reg";
reg { reg {
name = "Control Register"; name = "CR";
description = "Control Register";
prefix = "cr"; prefix = "cr";
field { field {
name = "CFGREGADR"; name = "Configuration register address";
description = "Address of FPGA configuration to read from"; description = "Address of FPGA configuration register to read.";
prefix = "cfgregadr"; prefix = "cfgregadr";
type = SLV; type = SLV;
size = 6; size = 6;
}; };
field { field {
name = "RDCFGREG"; name = "Read FPGA configuration register";
description = "Start FPGA configuration register sequence"; description = "1 -- Start FPGA configuration register sequence. \
0 -- No effect.";
prefix = "rdcfgreg"; prefix = "rdcfgreg";
type = MONOSTABLE; type = MONOSTABLE;
}; };
field { field {
name = "IPROG_UNLOCK"; name = "Unlock bit for the IPROG command";
description = "Unlocks IPROG bit"; description = "1 -- Unlock IPROG bit. \
0 -- No effect.";
prefix = "iprog_unlock"; prefix = "iprog_unlock";
type = BIT; type = BIT;
access_dev = READ_WRITE; access_dev = READ_WRITE;
...@@ -30,8 +33,11 @@ peripheral { ...@@ -30,8 +33,11 @@ peripheral {
align = 16; align = 16;
}; };
field { field {
name = "IPROG"; name = "Start IPROG sequence";
description = "Starts IPROG configuration sequence"; description = "1 -- Start IPROG configuration sequence \
0 -- No effect \
This bit needs to be unlocked by writing the IPROG_UNLOCK bit first. \
A write to this bit with IPROG_UNLOCK cleared has no effect.";
prefix = "iprog"; prefix = "iprog";
type = BIT; type = BIT;
access_dev = READ_WRITE; access_dev = READ_WRITE;
...@@ -41,11 +47,12 @@ peripheral { ...@@ -41,11 +47,12 @@ peripheral {
}; };
reg { reg {
name = "Status Register"; name = "SR";
description = "Status Register";
prefix = "sr"; prefix = "sr";
field { field {
name = "CFGREGIMG"; name = "Configuration register image";
description = "Image of the FPGA configuration register at address CFGREGADR"; description = "Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\\cite{ug380}); validated by IMGVALID bit";
prefix = "cfgregimg"; prefix = "cfgregimg";
type = SLV; type = SLV;
size = 16; size = 16;
...@@ -53,16 +60,18 @@ peripheral { ...@@ -53,16 +60,18 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
}; };
field { field {
name = "IMGVALID"; name = "Configuration register image valid";
description = "When '1', the image in CFGREGIMG is valid"; description = "1 -- CFGREGIMG valid \
0 -- CFGREGIMG not valid;";
prefix = "imgvalid"; prefix = "imgvalid";
type = BIT; type = BIT;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
access_bus = READ_ONLY; access_bus = READ_ONLY;
}; };
field { field {
name = "WDTO"; name = "MultiBoot FSM stalled at one point and was reset by FSM watchdog";
description = "When '1', the FSM watchdog in mutiboot_fsm has fired"; description = "1 -- FSM watchdog fired \
0 -- FSM watchdog has not fired";
prefix = "wdto"; prefix = "wdto";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
...@@ -72,13 +81,13 @@ peripheral { ...@@ -72,13 +81,13 @@ peripheral {
}; };
reg { reg {
name = "Golden Bitstream Base Address Register"; name = "GBBAR";
description = "Golden Bitstream Base Address Register";
prefix = "gbbar"; prefix = "gbbar";
field { field {
name = "GBBAR"; name = "Bits of GBBAR register";
description = "GBBAR \ description = "31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \
31..24 Read OPCODE of the flash chip \ 23..0 -- Golden bitstream address in flash";
23..0 Golden bitstream address in flash";
prefix = "bits"; prefix = "bits";
type = SLV; type = SLV;
size = 32; size = 32;
...@@ -86,13 +95,13 @@ peripheral { ...@@ -86,13 +95,13 @@ peripheral {
}; };
reg { reg {
name = "MultiBoot Bitstream Base Address Register"; name = "MBBAR";
description = "MultiBoot Bitstream Base Address Register";
prefix = "mbbar"; prefix = "mbbar";
field { field {
name = "MBBAR"; name = "Bits of MBBAR register";
description = "MBBAR \ description = "31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \
31..24 Read OPCODE of the flash chip \ 23..0 -- MultiBoot bitstream start address in flash";
23..0 MultiBoot bitstream address in flash";
prefix = "bits"; prefix = "bits";
type = SLV; type = SLV;
size = 32; size = 32;
...@@ -100,11 +109,14 @@ peripheral { ...@@ -100,11 +109,14 @@ peripheral {
}; };
reg { reg {
name = "Flash Access Register"; name = "FAR";
description = "Flash Access Register";
prefix = "far"; prefix = "far";
field { field {
name = "DATA"; name = "Flash data field";
description = "I/O flash data"; description = "23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \
15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \
7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash";
prefix = "data"; prefix = "data";
type = SLV; type = SLV;
size = 24; size = 24;
...@@ -113,32 +125,33 @@ peripheral { ...@@ -113,32 +125,33 @@ peripheral {
load = LOAD_EXT; load = LOAD_EXT;
}; };
field { field {
name = "NBYTES"; name = "Number of DATA fields to send and receive in one transfer:";
description = "Number of bytes to send to and receive from flash"; description = " 0x0 -- Send 1 byte (DATA[0]) \
0x1 -- Send 2 bytes (DATA[0], DATA[1]) \
0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])";
prefix = "nbytes"; prefix = "nbytes";
type = SLV; type = SLV;
size = 2; size = 2;
}; };
field { field {
name = "XFER"; name = "Start transfer to and from flash";
description = "Start transfer to and from flash"; description = "1 -- Start transfer \
0 -- Idle";
prefix = "xfer"; prefix = "xfer";
type = MONOSTABLE; type = MONOSTABLE;
size = 1; size = 1;
}; };
field { field {
name = "CS"; name = "Chip select bit";
description = "Chip select bit \ description = "1 - Flash chip selected (CS pin low) \
0 - Flash chip not selected (CS pin is high) \ 0 - Flash chip not selected (CS pin is high)";
1 - Flash chip selected (CS pin low)";
prefix = "cs"; prefix = "cs";
type = BIT; type = BIT;
}; };
field { field {
name = "READY"; name = "Flash access ready";
description = "Flash access ready bit \ description = "1 - Flash access completed \
0 - Flash access in progress \ 0 - Flash access in progress";
1 - Flash access completed";
prefix = "ready"; prefix = "ready";
type = BIT; type = BIT;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
......
platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
View file @ ef8a39f7
...@@ -82,41 +82,41 @@ architecture struct of wb_xil_multiboot is ...@@ -82,41 +82,41 @@ architecture struct of wb_xil_multiboot is
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'CFGREGADR' in reg: 'Control Register' -- Port for std_logic_vector field: 'Configuration register address' in reg: 'CR'
reg_cr_cfgregadr_o : out std_logic_vector(5 downto 0); reg_cr_cfgregadr_o : out std_logic_vector(5 downto 0);
-- Port for MONOSTABLE field: 'RDCFGREG' in reg: 'Control Register' -- Port for MONOSTABLE field: 'Read FPGA configuration register' in reg: 'CR'
reg_cr_rdcfgreg_o : out std_logic; reg_cr_rdcfgreg_o : out std_logic;
-- Port for BIT field: 'IPROG_UNLOCK' in reg: 'Control Register' -- Ports for BIT field: 'Unlock bit for the IPROG command' in reg: 'CR'
reg_cr_iprog_unlock_o : out std_logic; reg_cr_iprog_unlock_o : out std_logic;
reg_cr_iprog_unlock_i : in std_logic; reg_cr_iprog_unlock_i : in std_logic;
reg_cr_iprog_unlock_load_o : out std_logic; reg_cr_iprog_unlock_load_o : out std_logic;
-- Ports for BIT field: 'IPROG' in reg: 'Control Register' -- Ports for BIT field: 'Start IPROG sequence' in reg: 'CR'
reg_cr_iprog_o : out std_logic; reg_cr_iprog_o : out std_logic;
reg_cr_iprog_i : in std_logic; reg_cr_iprog_i : in std_logic;
reg_cr_iprog_load_o : out std_logic; reg_cr_iprog_load_o : out std_logic;
-- Port for std_logic_vector field: 'CFGREGIMG' in reg: 'Status Register' -- Port for std_logic_vector field: 'Configuration register image' in reg: 'SR'
reg_sr_cfgregimg_i : in std_logic_vector(15 downto 0); reg_sr_cfgregimg_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'IMGVALID' in reg: 'Status Register' -- Port for BIT field: 'Configuration register image valid' in reg: 'SR'
reg_sr_imgvalid_i : in std_logic; reg_sr_imgvalid_i : in std_logic;
-- Ports for BIT field: 'WDTO' in reg: 'Status Register' -- Ports for BIT field: 'MultiBoot FSM stalled at one point and was reset by FSM watchdog' in reg: 'SR'
reg_sr_wdto_o : out std_logic; reg_sr_wdto_o : out std_logic;
reg_sr_wdto_i : in std_logic; reg_sr_wdto_i : in std_logic;
reg_sr_wdto_load_o : out std_logic; reg_sr_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'GBBAR' in reg: 'Golden Bitstream Base Address Register' -- Port for std_logic_vector field: 'Bits of GBBAR register' in reg: 'GBBAR'
reg_gbbar_bits_o : out std_logic_vector(31 downto 0); reg_gbbar_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MBBAR' in reg: 'MultiBoot Bitstream Base Address Register' -- Port for std_logic_vector field: 'Bits of MBBAR register' in reg: 'MBBAR'
reg_mbbar_bits_o : out std_logic_vector(31 downto 0); reg_mbbar_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'DATA' in reg: 'Flash Access Register' -- Port for std_logic_vector field: 'Flash data field' in reg: 'FAR'
reg_far_data_o : out std_logic_vector(23 downto 0); reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_data_i : in std_logic_vector(23 downto 0); reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_load_o : out std_logic; reg_far_data_load_o : out std_logic;
-- Port for std_logic_vector field: 'NBYTES' in reg: 'Flash Access Register' -- Port for std_logic_vector field: 'Number of DATA fields to send and receive in one transfer:' in reg: 'FAR'
reg_far_nbytes_o : out std_logic_vector(1 downto 0); reg_far_nbytes_o : out std_logic_vector(1 downto 0);
-- Port for MONOSTABLE field: 'XFER' in reg: 'Flash Access Register' -- Port for MONOSTABLE field: 'Start transfer to and from flash' in reg: 'FAR'
reg_far_xfer_o : out std_logic; reg_far_xfer_o : out std_logic;
-- Port for BIT field: 'CS' in reg: 'Flash Access Register' -- Port for BIT field: 'Chip select bit' in reg: 'FAR'
reg_far_cs_o : out std_logic; reg_far_cs_o : out std_logic;
-- Port for BIT field: 'READY' in reg: 'Flash Access Register' -- Port for BIT field: 'Flash access ready' in reg: 'FAR'
reg_far_ready_i : in std_logic reg_far_ready_i : in std_logic
); );
end component multiboot_regs; end component multiboot_regs;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment