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b814d633
Commit
b814d633
authored
Jul 29, 2019
by
Dimitris Lampridis
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[hdl] code cleanup of gc_frequency_meter
parent
686760c9
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2 changed files
with
60 additions
and
63 deletions
+60
-63
gc_frequency_meter.vhd
modules/common/gc_frequency_meter.vhd
+56
-59
gencores_pkg.vhd
modules/common/gencores_pkg.vhd
+4
-4
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modules/common/gc_frequency_meter.vhd
View file @
b814d633
-------------------------------------------------------------------------------
-- Title : Frequency meter
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : gc_frequency_meter.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2012-2015 CERN
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- General Cores Library
-- https://www.ohwr.org/projects/general-cores
--------------------------------------------------------------------------------
--
-- unit name: gc_frequency_meter
--
-- description: Frequency meter with internal or external timebase.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2012-2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--
“AS IS”
BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
--
"AS IS"
BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
library
ieee
;
...
...
@@ -31,43 +31,41 @@ library work;
use
work
.
gencores_pkg
.
all
;
entity
gc_frequency_meter
is
generic
(
g_
with_internal_timebase
:
boolean
:
=
true
;
g_
clk_sys_freq
:
integer
;
generic
(
g_
WITH_INTERNAL_TIMEBASE
:
boolean
:
=
TRUE
;
g_
CLK_SYS_FREQ
:
integer
;
-- if true, sync freq_o to the clk_sys domain
g_SYNC_OUT
:
boolean
:
=
false
;
g_counter_bits
:
integer
:
=
32
);
port
(
g_SYNC_OUT
:
boolean
:
=
FALSE
;
g_COUNTER_BITS
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
clk_in_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- not used, kept for backward compatibility
rst_n_i
:
in
std_logic
;
-- not used, kept for backward compatibility
pps_p1_i
:
in
std_logic
;
-- synced to clk_in_i or clk_sys_i, depending on g_SYNC_OUT value
freq_o
:
out
std_logic_vector
(
g_
counter_bits
-1
downto
0
);
freq_o
:
out
std_logic_vector
(
g_
COUNTER_BITS
-1
downto
0
);
-- synced to clk_sys_i, always
freq_valid_o
:
out
std_logic
);
freq_valid_o
:
out
std_logic
);
end
gc_frequency_meter
;
architecture
behavioral
of
gc_frequency_meter
is
architecture
arch
of
gc_frequency_meter
is
signal
gate_pulse
,
gate_pulse_synced
:
std_logic
:
=
'0'
;
signal
cntr_gate
:
unsigned
(
g_counter_bits
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
cntr_meas
:
unsigned
(
g_counter_bits
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
freq_reg
:
std_logic_vector
(
g_counter_bits
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
cntr_gate
:
unsigned
(
g_COUNTER_BITS
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
cntr_meas
:
unsigned
(
g_COUNTER_BITS
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
freq_reg
:
std_logic_vector
(
g_COUNTER_BITS
-1
downto
0
)
:
=
(
others
=>
'0'
);
begin
gen_internal_timebase
:
if
(
g_with_internal_timebase
=
true
)
generate
gen_internal_timebase
:
if
g_WITH_INTERNAL_TIMEBASE
=
TRUE
generate
p_gate_counter
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
cntr_gate
=
g_clk_sys_freq
-1
)
then
if
cntr_gate
=
g_CLK_SYS_FREQ
-1
then
cntr_gate
<=
(
others
=>
'0'
);
gate_pulse
<=
'1'
;
else
...
...
@@ -77,36 +75,35 @@ begin
end
if
;
end
process
;
U_Sync_Gate
:
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_in_i
,
rst_n_i
=>
'1'
,
d_ready_o
=>
freq_valid_o
,
d_p_i
=>
gate_pulse
,
q_p_o
=>
gate_pulse_synced
);
U_Sync_Gate
:
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_in_i
,
rst_n_i
=>
'1'
,
d_ready_o
=>
freq_valid_o
,
d_p_i
=>
gate_pulse
,
q_p_o
=>
gate_pulse_synced
);
end
generate
gen_internal_timebase
;
gen_external_timebase
:
if
(
g_with_internal_timebase
=
false
)
generate
gen_external_timebase
:
if
g_WITH_INTERNAL_TIMEBASE
=
FALSE
generate
U_Sync_Gate
:
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_in_i
,
rst_n_i
=>
'1'
,
d_ready_o
=>
freq_valid_o
,
d_p_i
=>
pps_p1_i
,
q_p_o
=>
gate_pulse_synced
);
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_in_i
,
rst_n_i
=>
'1'
,
d_ready_o
=>
freq_valid_o
,
d_p_i
=>
pps_p1_i
,
q_p_o
=>
gate_pulse_synced
);
end
generate
gen_external_timebase
;
p_freq_counter
:
process
(
clk_in_i
,
rst_n_i
)
p_freq_counter
:
process
(
clk_in_i
)
begin
if
rising_edge
(
clk_in_i
)
then
if
(
gate_pulse_synced
=
'1'
)
then
if
gate_pulse_synced
=
'1'
then
freq_reg
<=
std_logic_vector
(
cntr_meas
);
cntr_meas
<=
(
others
=>
'0'
);
else
...
...
@@ -115,8 +112,8 @@ begin
end
if
;
end
process
p_freq_counter
;
gen_with_sync_out
:
if
g_SYNC_OUT
generate
cmp_gc_sync_word_wr
:
gc_sync_word_wr
gen_with_sync_out
:
if
g_SYNC_OUT
generate
cmp_gc_sync_word_wr
:
gc_sync_word_wr
generic
map
(
g_AUTO_WR
=>
TRUE
,
g_WIDTH
=>
g_COUNTER_BITS
)
...
...
@@ -129,8 +126,8 @@ begin
data_o
=>
freq_o
);
end
generate
gen_with_sync_out
;
gen_without_sync_out
:
if
not
g_SYNC_OUT
generate
gen_without_sync_out
:
if
not
g_SYNC_OUT
generate
freq_o
<=
freq_reg
;
end
generate
gen_without_sync_out
;
end
behavioral
;
end
arch
;
modules/common/gencores_pkg.vhd
View file @
b814d633
...
...
@@ -251,16 +251,16 @@ package gencores_pkg is
------------------------------------------------------------------------------
component
gc_frequency_meter
generic
(
g_
with_internal_timebase
:
boolean
;
g_
clk_sys_freq
:
integer
;
g_
WITH_INTERNAL_TIMEBASE
:
boolean
:
=
TRUE
;
g_
CLK_SYS_FREQ
:
integer
;
g_SYNC_OUT
:
boolean
:
=
FALSE
;
g_
counter_bits
:
integer
);
g_
COUNTER_BITS
:
integer
);
port
(
clk_sys_i
:
in
std_logic
;
clk_in_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pps_p1_i
:
in
std_logic
;
freq_o
:
out
std_logic_vector
(
g_
counter_bits
-1
downto
0
);
freq_o
:
out
std_logic_vector
(
g_
COUNTER_BITS
-1
downto
0
);
freq_valid_o
:
out
std_logic
);
end
component
;
...
...
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