[hdl] add g_SYNC_OUT option to gc_frequency meter.

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain. With the new option, if set to TRUE, both outputs will be in the system clock domain.

[hdl] add g_SYNC_OUT option to gc_frequency meter.
Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain. With the new option, if set to TRUE, both outputs will be in the system clock domain.
686760c9 · Dimitris Lampridis · 13cebbbd · 686760c9 · 686760c9
Commit 686760c9 authored Jul 29, 2019 by Dimitris Lampridis
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Showing with 23 additions and 3 deletions

gc_frequency_meter.vhd modules/common/gc_frequency_meter.vhd +22 -3

gencores_pkg.vhd modules/common/gencores_pkg.vhd +1 -0

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--- a/modules/common/gc_frequency_meter.vhd
+++ b/modules/common/gc_frequency_meter.vhd
@@ -34,6 +34,8 @@ entity gc_frequency_meter is
  generic(
    g_with_internal_timebase : boolean := true;
    g_clk_sys_freq           : integer;
+    -- if true, sync freq_o to the clk_sys domain
+    g_SYNC_OUT               : boolean := false;
    g_counter_bits           : integer := 32);

  port(
@@ -41,7 +43,9 @@ entity gc_frequency_meter is
    clk_in_i     : in  std_logic;
    rst_n_i      : in  std_logic; -- not used, kept for backward compatibility
    pps_p1_i     : in  std_logic;
+    -- synced to clk_in_i or clk_sys_i, depending on g_SYNC_OUT value
    freq_o       : out std_logic_vector(g_counter_bits-1 downto 0);
+    -- synced to clk_sys_i, always
    freq_valid_o : out std_logic
    );

@@ -111,7 +115,22 @@ begin
    end if;
  end process p_freq_counter;

-  freq_o <= freq_reg;
-end behavioral;
-
+  gen_with_sync_out: if g_SYNC_OUT generate
+    cmp_gc_sync_word_wr: gc_sync_word_wr
+      generic map (
+        g_AUTO_WR => TRUE,
+        g_WIDTH   => g_COUNTER_BITS)
+      port map (
+        clk_in_i    => clk_in_i,
+        rst_in_n_i  => '1',
+        clk_out_i   => clk_sys_i,
+        rst_out_n_i => '1',
+        data_i      => freq_reg,
+        data_o      => freq_o);
+  end generate gen_with_sync_out;
+
+  gen_without_sync_out: if not g_SYNC_OUT generate
+    freq_o <= freq_reg;
+  end generate gen_without_sync_out;

+end behavioral;
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -253,6 +253,7 @@ package gencores_pkg is
    generic (
      g_with_internal_timebase : boolean;
      g_clk_sys_freq           : integer;
+      g_SYNC_OUT               : boolean := FALSE;
      g_counter_bits           : integer);
    port (
      clk_sys_i    : in  std_logic;