gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI…

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed together

gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI…
gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed together
b694c67c · Tomasz Wlostowski · Tristan Gingold · 2d29017e · b694c67c
Commit b694c67c authored May 13, 2020 by Tomasz Wlostowski Committed by Tristan Gingold Sep 09, 2020
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gc_simple_spi_master.vhd modules/common/gc_simple_spi_master.vhd +2 -1

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--- a/modules/common/gc_simple_spi_master.vhd
+++ b/modules/common/gc_simple_spi_master.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2013-01-25
+-- Last update: 2020-05-05
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -129,6 +129,7 @@ begin  -- rtl
          -- Waits for start of transfer command
          when IDLE =>
            sclk    <= '0';
+            spi_mosi_o <= '0';
            counter <= (others => '0');
            if(start_i = '1') then
              sreg            <= data_i;