wb_fine_pulse_gen: fix incorrect reset signal for IDELAYCTRL for Ultrascale devices

a68a932b · Tomasz Wlostowski · 605b1e25 · a68a932b
Commit a68a932b authored Aug 09, 2021 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 1 addition and 1 deletion

fine_pulse_gen_kintexultrascale_shared.vhd ...fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd +1 -1

No files found.
--- a/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
+++ b/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
@@ -165,7 +165,7 @@ begin
      port map (
        RDY    => odelayctrl_rdy_o,
        REFCLK => clk_odelay,    
-        RST    => odelayctrl_rst_i
+        RST    => rst_synced
        );
    end block;
  end generate gen_use_odelay;