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Platform-independent core collection
Commit 907c58d0 authored by kblantos's avatar kblantos
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Fix the tab spaces in gc_delay_gen

parent 43171532
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Showing with 33 additions and 33 deletions
testbench/common/gc_delay_gen/tb_gc_delay_gen.vhd
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......@@ -14,20 +14,20 @@
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -46,7 +46,7 @@ library osvvm;
use osvvm.RandomPkg.all;
use osvvm.CoveragePkg.all;
entity tb_gc_delay_gen is
entity tb_gc_delay_gen is
generic (
g_seed : natural;
g_delay_cycles : natural := 2;
......@@ -63,7 +63,7 @@ architecture tb of tb_gc_delay_gen is
signal tb_rst_n_i : std_logic;
signal tb_d_i : std_logic_vector(g_data_width-1 downto 0);
signal tb_q_o : std_logic_vector(g_data_width-1 downto 0);
type t_dly_array is array (0 to g_delay_cycles) of std_logic_vector(g_data_width -1 downto 0);
signal s_dly_arr : t_dly_array;
......@@ -101,7 +101,7 @@ begin
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
......@@ -115,37 +115,37 @@ begin
stop <= TRUE;
wait;
end process stim;
--------------------------------------------------------------------------------
-- Assertions - Self Checking --
--------------------------------------------------------------------------------
-- Fill the array with input data
delay_array : process (tb_clk_i, tb_rst_n_i)
begin
if tb_rst_n_i = '0' then
begin
if tb_rst_n_i = '0' then
for_rst : for i in 1 to g_delay_cycles loop
s_dly_arr(i) <= (others => '0');
end loop;
elsif rising_edge(tb_clk_i) then
s_dly_arr(i) <= (others => '0');
end loop;
elsif rising_edge(tb_clk_i) then
s_dly_arr(0) <= tb_d_i;
for_clk : for i in 0 to g_delay_cycles-1 loop
s_dly_arr(i+1) <= s_dly_arr(i);
end loop;
for_clk : for i in 0 to g_delay_cycles-1 loop
s_dly_arr(i+1) <= s_dly_arr(i);
end loop;
end if;
end process delay_array;
end process delay_array;
--Depending on the g_delay_cycles, we expect the output equal to input
self_check : process(tb_clk_i)
begin
if rising_edge(tb_clk_i) and tb_rst_n_i = '1' then
assert (s_dly_arr(g_delay_cycles) = tb_q_o)
report "Data mismatch" severity failure;
end if;
assert (s_dly_arr(g_delay_cycles) = tb_q_o)
report "Data mismatch" severity failure;
end if;
end process;
end tb;
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