Commit 43171532 authored by kblantos's avatar kblantos

Minor fixes in some Common Cores

parent 7a9aa82a
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Title : AXI4Full64 to AXI4Lite32 bridge
-- Project : General Cores
-------------------------------------------------------------------------------
......@@ -27,8 +27,8 @@ use ieee.numeric_std.all;
entity axi4lite32_axi4full64_bridge is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- AXI4-Full slave
s_awaddr : in STD_LOGIC_VECTOR (31 downto 0);
......@@ -99,15 +99,15 @@ architecture behav of axi4lite32_axi4full64_bridge is
signal wstate : t_wr_state;
signal rstate : t_rd_state;
signal waddr : std_logic_vector(31 downto 0);
signal wlen : std_logic_vector(7 downto 0);
signal wsize : std_logic_vector(2 downto 0);
signal waddr : std_logic_vector(31 downto 0);
signal wlen : std_logic_vector(7 downto 0);
signal wsize : std_logic_vector(2 downto 0);
signal wdata : std_logic_vector(63 downto 0);
signal wstrb : std_logic_vector(7 downto 0);
signal wstrb : std_logic_vector(7 downto 0);
signal raddr : std_logic_vector(31 downto 0);
signal rlen : std_logic_vector(7 downto 0);
signal rsize : std_logic_vector(2 downto 0);
signal raddr : std_logic_vector(31 downto 0);
signal rlen : std_logic_vector(7 downto 0);
signal rsize : std_logic_vector(2 downto 0);
signal rdata : std_logic_vector(63 downto 0);
begin
-- Write part.
......@@ -240,7 +240,6 @@ begin
rstate <= RD_IDLE;
s_arready <= '1';
s_rvalid <= '0';
s_rlast <= '0';
m_arvalid <= '0';
m_rready <= '0';
raddr <= (others => 'X');
......@@ -290,17 +289,13 @@ begin
-- To master.
rstate <= RD_SLAVE;
s_rresp <= RSP_OKAY;
if rlen = x"00" then
s_rlast <= '1';
else
s_rlast <= '0';
end if;
m_rready <= '0';
s_rvalid <= '1';
else
-- Next transfer.
raddr (2) <= '1';
m_arvalid <= '1';
m_rready <= '1';
m_arvalid <= '1';
m_rready <= '1';
end if;
end if;
......@@ -317,8 +312,8 @@ begin
-- TODO: adjust address.
-- New beat.
m_arvalid <= '1';
m_rready <= '1';
m_arvalid <= '1';
m_rready <= '1';
rstate <= RD_READ;
end if;
end if;
......@@ -326,4 +321,7 @@ begin
end if;
end if;
end process;
s_rlast <= '1' when (rlen=x"00" and s_rready='1') else '0';
end behav;
-------------------------------------------------------------------------------
-- Title : AXI4Full64 to AXI4Lite32 bridge
-- Title : AXI4Lite to AXI4Full bridge
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : axi4lite32_axi4full64_bridge.vhd
-- File : axi4lite_axi4full_bridge.vhd
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
......@@ -233,6 +233,9 @@ begin
s_rdata <= rdata;
s_rid <= rid;
s_rlast <= '1' when (unsigned(rlen)=0 and s_rready = '1' and s_rvalid = '1')
else '0';
process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -240,7 +243,7 @@ begin
rstate <= RD_IDLE;
s_arready <= '1';
s_rvalid <= '0';
s_rlast <= '0';
-- s_rlast <= '0';
m_arvalid <= '0';
m_rready <= '0';
raddr <= (others => 'X');
......@@ -275,6 +278,7 @@ begin
m_arvalid <= '0';
end if;
if m_rvalid = '1' then
m_rready <= '0';
-- Read data. Address must have been acked.
-- According to A3.4.3 of AXI4 spec, the AXI4 bus is little
-- endian.
......@@ -283,11 +287,11 @@ begin
-- To master.
rstate <= RD_SLAVE;
s_rresp <= RSP_OKAY;
if rlen = (g_LEN_WIDTH - 1 downto 0 => '0') then
s_rlast <= '1';
else
s_rlast <= '0';
end if;
-- if rlen = (g_LEN_WIDTH - 1 downto 0 => '0') then
-- s_rlast <= '1';
-- else
-- s_rlast <= '0';
-- end if;
s_rvalid <= '1';
end if;
......@@ -314,3 +318,4 @@ begin
end if;
end process;
end behav;
......@@ -42,4 +42,5 @@ files = [
"gc_async_counter_diff.vhd",
"gc_sync_word_wr.vhd",
"gc_sync_word_rd.vhd",
"gc_simple_spi_master.vhd"
];
......@@ -183,7 +183,6 @@ begin -- behavioral
pi_state <= PI_CHECK_MODE;
dac_val_stb_p_o <= '0';
dac_val_int <= std_logic_vector(to_unsigned(g_output_bias, dac_val_int'length));
freq_mode <= '1';
else
case pi_state is
......@@ -205,10 +204,10 @@ begin -- behavioral
dac_val_stb_p_o <= '0';
pi_state <= PI_WAIT_SAMPLE;
else
dac_val_stb_p_o <= '1';
dac_val_int <= std_logic_vector(to_unsigned(g_output_bias, dac_val_int'length));
dac_val_stb_p_o <= '1';
dac_val_int <= std_logic_vector(to_unsigned(g_output_bias, dac_val_int'length));
pi_state <= PI_DISABLED;
freq_mode <= '1';
freq_mode <= '1';
end if;
-------------------------------------------------------------------------------
......
......@@ -42,7 +42,7 @@ entity gc_multichannel_frequency_meter is
clk_in_i : in std_logic_vector(g_CHANNELS -1 downto 0);
rst_n_i : in std_logic;
pps_p1_i : in std_logic;
channel_sel_i : in std_logic_vector(3 downto 0);
channel_sel_i : in std_logic_vector(f_log2_ceil(g_CHANNELS)-1 downto 0);
freq_o : out std_logic_vector(g_COUNTER_BITS-1 downto 0);
freq_valid_o : out std_logic
);
......@@ -65,6 +65,7 @@ architecture arch of gc_multichannel_frequency_meter is
type t_channel_state_array is array(0 to g_CHANNELS-1) of t_channel_state;
signal ch : t_channel_state_array;
signal idx : integer range 0 to g_CHANNELS+1;
begin
......@@ -121,17 +122,18 @@ begin
ch(i).cntr <= (others => '0');
else
ch(i).cntr <= ch(i).cntr + 1;
ch(i).freq_valid <= '0';
end if;
end if;
end process p_freq_counter;
end generate gen_channels;
idx <= to_integer(unsigned(channel_sel_i));
p_freq_output : process(clk_sys_i)
variable idx : integer range 0 to g_CHANNELS-1;
begin
if rising_edge(clk_sys_i) then
idx := to_integer(unsigned(channel_sel_i));
freq_o <= std_logic_vector(ch(idx).freq);
freq_valid_o <= ch(idx).freq_valid;
end if;
......
......@@ -11,7 +11,7 @@ echo "*When g_WITH_INTERNAL_TIMEBASE = TRUE*"
echo "======================================"
echo "clk_sys_freq = 500, sync_out = TRUE, counter_bits=32"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_WITH_INTERNAL_TIMEBASE=TRUE -gg_CLK_SYS_FREQ=500 -gg_CHANNELS=2 -gg_COUNTER_BITS=32
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_WITH_INTERNAL_TIMEBASE=TRUE -gg_CLK_SYS_FREQ=500 -gg_CHANNELS=2 -gg_COUNTER_BITS=32
echo "******************************************************************************"
echo "clk_sys_freq = 1000, sync_out = FALSE, counter_bits=32"
......
......@@ -248,7 +248,7 @@ begin
assert (g_CHANNELS > 1)
report "Invalid number of channels" severity failure;
-- Check if output is the expected, for TRUE it is OK
-- Check if output is the expected
check_output : process(tb_clk_sys_i)
begin
if (rising_edge(tb_clk_sys_i) and tb_rst_n_i = '1') then
......
......@@ -6,4 +6,4 @@ TB=tb_gc_pulse_synchronizer2
echo "Running simulation for $TB"
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM
ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM --wave=waveform.ghw
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