genram: add a "dont_care" option for g_addr_conflict_resolution

The RW ordering on address conflict varies by platform. Some platforms only support some options. Most of the dprams in WR are portable and don't depend on the order. This new option allows a core to specify that it does not care what the result of a RW conflict is, and thus work on more platforms. For Xilinx, "dont_care" = "read_first", the old default.

genram: add a "dont_care" option for g_addr_conflict_resolution
The RW ordering on address conflict varies by platform. Some platforms only support some options. Most of the dprams in WR are portable and don't depend on the order. This new option allows a core to specify that it does not care what the result of a RW conflict is, and thus work on more platforms. For Xilinx, "dont_care" = "read_first", the old default.
7df80bd4 · Wesley W. Terpstra · 3b80b62b · 7df80bd4 · 7df80bd4 · 7df80bd4
Commit 7df80bd4 authored Mar 05, 2013 by Wesley W. Terpstra
5 changed files
--- a/modules/genrams/genram_pkg.vhd
+++ b/modules/genrams/genram_pkg.vhd
@@ -53,7 +53,7 @@ package genram_pkg is
      g_size                     : natural;
      g_with_byte_enable         : boolean := false;
      g_init_file                : string  := "";
-      g_addr_conflict_resolution : string  := "read_first") ;
+      g_addr_conflict_resolution : string  := "dont_care") ;
    port (
      rst_n_i : in  std_logic;
      clk_i   : in  std_logic;
@@ -69,7 +69,7 @@ package genram_pkg is
      g_data_width               : natural;
      g_size                     : natural;
      g_with_byte_enable         : boolean := false;
-      g_addr_conflict_resolution : string  := "read_first";
+      g_addr_conflict_resolution : string  := "dont_care";
      g_init_file                : string  := "none";
      g_dual_clock               : boolean := true);
    port (
@@ -89,7 +89,7 @@ package genram_pkg is
      g_data_width               : natural;
      g_size                     : natural;
      g_with_byte_enable         : boolean := false;
-      g_addr_conflict_resolution : string  := "read_first";
+      g_addr_conflict_resolution : string  := "dont_care";
      g_init_file                : string  := "";
      g_dual_clock               : boolean := true);
    port (

--- a/modules/genrams/xilinx/generic_dpram_dualclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -123,7 +123,8 @@ begin
  s_we_a <= bwea_i and wea_rep;
  s_we_b <= bweb_i and web_rep;

-  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate


    process (clka_i)
@@ -159,7 +160,8 @@ begin



-  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate

    process(clka_i)
    begin

--- a/modules/genrams/xilinx/generic_dpram_sameclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_sameclock.vhd
@@ -120,7 +120,8 @@ begin
  s_we_a <= bwea_i and wea_rep;
  s_we_b <= bweb_i and web_rep;

-  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate

    process (clk_i)
    begin
@@ -142,7 +143,8 @@ begin



-  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate

    process(clk_i)
    begin

--- a/modules/genrams/xilinx/generic_spram.vhd
+++ b/modules/genrams/xilinx/generic_spram.vhd
@@ -115,7 +115,8 @@ begin

  end generate gen_with_byte_enable_writefirst;

-  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
+  gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
+                                                                     g_addr_conflict_resolution = "dont_care")) generate
    s_we <= bwe_i when we_i = '1' else (others => '0');

    process(s_we, d_i)
@@ -155,7 +156,8 @@ begin

  end generate gen_without_byte_enable_writefirst;

-  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
+  gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
+                                                                         g_addr_conflict_resolution = "dont_care")) generate

    process(clk_i)
    begin

--- a/modules/wishbone/wb_dpram/xwb_dpram.vhd
+++ b/modules/wishbone/wb_dpram/xwb_dpram.vhd
@@ -114,7 +114,7 @@ begin
      g_data_width               => 32,
      g_size                     => g_size,
      g_with_byte_enable         => true,
-      g_addr_conflict_resolution => "read_first",
+      g_addr_conflict_resolution => "dont_care",
      g_init_file                => g_init_file,
      g_dual_clock               => false
      )