genram: add a generic_simple_dpram

On both Altera and Xilinx, a dual port memory can achieve twice the bit-width per memory block when there is a single reader and writer. This adds a place-holder generic_simple_dpram for Xilinx so that code using the purpose-built variant for Altera continues to work on ISE.

genram: add a generic_simple_dpram
On both Altera and Xilinx, a dual port memory can achieve twice the bit-width per memory block when there is a single reader and writer. This adds a place-holder generic_simple_dpram for Xilinx so that code using the purpose-built variant for Altera continues to work on ISE.
3b80b62b · Wesley W. Terpstra · fb24703c · 3b80b62b · 3b80b62b · 3b80b62b
Commit 3b80b62b authored Mar 05, 2013 by Wesley W. Terpstra
Showing with 120 additions and 0 deletions

genram_pkg.vhd modules/genrams/genram_pkg.vhd +20 -0

Manifest.py modules/genrams/xilinx/Manifest.py +1 -0

generic_simple_dpram.vhd modules/genrams/xilinx/generic_simple_dpram.vhd +99 -0

No files found.
--- a/modules/genrams/genram_pkg.vhd
+++ b/modules/genrams/genram_pkg.vhd
@@ -64,6 +64,26 @@ package genram_pkg is
      q_o     : out std_logic_vector(g_data_width-1 downto 0));
  end component;

+  component generic_simple_dpram
+    generic (
+      g_data_width               : natural;
+      g_size                     : natural;
+      g_with_byte_enable         : boolean := false;
+      g_addr_conflict_resolution : string  := "read_first";
+      g_init_file                : string  := "none";
+      g_dual_clock               : boolean := true);
+    port (
+      rst_n_i : in  std_logic := '1';
+      clka_i  : in  std_logic;
+      bwea_i  : in  std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
+      wea_i   : in  std_logic;
+      aa_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      da_i    : in  std_logic_vector(g_data_width       -1 downto 0);
+      clkb_i  : in  std_logic;
+      ab_i    : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      qb_o    : out std_logic_vector(g_data_width       -1 downto 0));
+  end component;
+
  component generic_dpram
    generic (
      g_data_width               : natural;

--- a/modules/genrams/xilinx/Manifest.py
+++ b/modules/genrams/xilinx/Manifest.py
@@ -2,5 +2,6 @@ files = [
 "generic_dpram.vhd",
 "generic_dpram_sameclock.vhd",
 "generic_dpram_dualclock.vhd",
+"generic_simple_dpram.vhd",
 "generic_spram.vhd"
 ]
--- a/modules/genrams/xilinx/generic_simple_dpram.vhd
+++ b/modules/genrams/xilinx/generic_simple_dpram.vhd
+-------------------------------------------------------------------------------
+-- Title      : Parametrizable dual-port synchronous RAM (Xilinx version)
+-- Project    : Generics RAMs and FIFOs collection
+-------------------------------------------------------------------------------
+-- File       : generic_simple_dpram.vhd
+-- Author     : Wesley W. Terpstra
+-- Company    : GSI
+-- Created    : 2013-03-04
+-- Last update: 2013-03-04
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+-- - configurable address and data bus width
+-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
+-- Todo:
+-- - loading initial contents from file
+-- - add support for read-first/write-first address conflict resulution (only
+--   supported by Xilinx in VHDL templates)
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-04  1.0      wterpstra       Initial version: wrapper to generic_dpram
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.genram_pkg.all;
+use work.memory_loader_pkg.all;
+
+entity generic_simple_dpram is
+
+  generic (
+    -- standard parameters
+    g_data_width : natural := 32;
+    g_size       : natural := 16384;
+
+    g_with_byte_enable         : boolean := false;
+    g_addr_conflict_resolution : string  := "read_first";
+    g_init_file                : string  := "";
+    g_dual_clock               : boolean := true;
+    g_fail_if_file_not_found   : boolean := true
+    );
+
+  port (
+    rst_n_i : in std_logic := '1';      -- synchronous reset, active LO
+
+    -- Port A
+    clka_i : in  std_logic;
+    bwea_i : in  std_logic_vector((g_data_width+7)/8-1 downto 0);
+    wea_i  : in  std_logic;
+    aa_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    da_i   : in  std_logic_vector(g_data_width-1 downto 0);
+    
+    -- Port B
+    clkb_i : in  std_logic;
+    ab_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0);
+    qb_o   : out std_logic_vector(g_data_width-1 downto 0)
+    );
+
+end generic_simple_dpram;
+
+
+
+architecture syn of generic_simple_dpram is
+begin
+
+  -- Works well enough until a Xilinx guru can optimize it.
+  true_dp : generic_dpram
+    generic map(
+      g_data_width               => g_data_width,
+      g_size                     => g_size,
+      g_with_byte_enable         => g_with_byte_enable,
+      g_addr_conflict_resolution => g_addr_conflict_resolution,
+      g_init_file                => g_init_file,
+      g_dual_clock               => g_dual_clock)
+    port map(
+      rst_n_i => rst_n_i,
+      clka_i  => clka_i,
+      bwea_i  => bwea_i,
+      wea_i   => wea_i,
+      aa_i    => aa_i,
+      da_i    => da_i,
+      qa_o    => open,
+      clkb_i  => clkb_i,
+      bweb_i  => (others => '0'),
+      web_i   => '0',
+      ab_i    => ab_i,
+      db_i    => (others => '0'),
+      qb_o    => qb_o);
+
+end syn;