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Wesley W. Terpstra authored
On both Altera and Xilinx, a dual port memory can achieve twice the bit-width per memory block when there is a single reader and writer. This adds a place-holder generic_simple_dpram for Xilinx so that code using the purpose-built variant for Altera continues to work on ISE.
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| sim | ||
| syn/gsi_pexaria2a/wishbone_demo | ||
| testbench/wishbone | ||
| top/gsi_pexaria2a/wishbone_demo | ||
| .gitignore | ||
| Manifest.py | ||
| README |