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Platform-independent core collection
Commit 28cd7560 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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genrams: conditionally generate CDC synchronisers for async_fifos. 

This is beneficial because the gc_sync_ffs has a Xilinx "keep" attribute, which prevents the tools
from trimming out unused logic, even when the user has set the relevant generics to "FALSE".
parent 67d353ad
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Showing with 91 additions and 74 deletions
modules/genrams/common/inferred_async_fifo.vhd
View file @ 28cd7560
...@@ -124,11 +124,11 @@ architecture syn of inferred_async_fifo is ...@@ -124,11 +124,11 @@ architecture syn of inferred_async_fifo is
signal wr_count, rd_count : t_counter; signal wr_count, rd_count : t_counter;
signal rd_int, we_int : std_logic; signal rd_int, we_int : std_logic;
signal wr_empty_x : std_logic; signal wr_empty_x : std_logic := '0';
signal rd_full_x : std_logic; signal rd_full_x : std_logic := '0';
signal almost_full_x : std_logic; signal almost_full_x : std_logic := '0';
signal almost_empty_x : std_logic; signal almost_empty_x : std_logic := '0';
signal q_int : std_logic_vector(g_data_width-1 downto 0) := (others => '0'); signal q_int : std_logic_vector(g_data_width-1 downto 0) := (others => '0');
...@@ -225,23 +225,27 @@ begin -- syn ...@@ -225,23 +225,27 @@ begin -- syn
end if; end if;
end process p_gen_empty; end process p_gen_empty;
U_Sync_Empty : gc_sync_ffs gen_with_wr_empty : if g_with_wr_empty = TRUE generate
generic map ( U_Sync_Empty : gc_sync_ffs
g_sync_edge => "positive") generic map (
port map ( g_sync_edge => "positive")
clk_i => clk_wr_i, port map (
rst_n_i => rst_n_i, clk_i => clk_wr_i,
data_i => empty_int, rst_n_i => rst_n_i,
synced_o => wr_empty_x); data_i => empty_int,
synced_o => wr_empty_x);
U_Sync_Full : gc_sync_ffs end generate gen_with_wr_empty;
generic map (
g_sync_edge => "positive") gen_with_rd_full : if g_with_rd_full = TRUE generate
port map ( U_Sync_Full : gc_sync_ffs
clk_i => clk_rd_i, generic map (
rst_n_i => rst_n_i, g_sync_edge => "positive")
data_i => full_int, port map (
synced_o => rd_full_x); clk_i => clk_rd_i,
rst_n_i => rst_n_i,
data_i => full_int,
synced_o => rd_full_x);
end generate gen_with_rd_full;
rd_empty_o <= empty_int; rd_empty_o <= empty_int;
wr_empty_o <= wr_empty_x; wr_empty_o <= wr_empty_x;
...@@ -286,14 +290,16 @@ begin -- syn ...@@ -286,14 +290,16 @@ begin -- syn
end if; end if;
end process p_reg_almost_full; end process p_reg_almost_full;
U_Sync_AlmostFull : gc_sync_ffs gen_with_rd_almost_full : if g_with_rd_almost_full = TRUE generate
generic map ( U_Sync_AlmostFull : gc_sync_ffs
g_sync_edge => "positive") generic map (
port map ( g_sync_edge => "positive")
clk_i => clk_rd_i, port map (
rst_n_i => rst_n_i, clk_i => clk_rd_i,
data_i => almost_full_int, rst_n_i => rst_n_i,
synced_o => almost_full_x); data_i => almost_full_int,
synced_o => almost_full_x);
end generate gen_with_rd_almost_full;
wr_almost_full_o <= almost_full_int; wr_almost_full_o <= almost_full_int;
rd_almost_full_o <= almost_full_x; rd_almost_full_o <= almost_full_x;
...@@ -312,14 +318,16 @@ begin -- syn ...@@ -312,14 +318,16 @@ begin -- syn
end if; end if;
end process p_reg_almost_empty; end process p_reg_almost_empty;
U_Sync_AlmostEmpty : gc_sync_ffs gen_with_wr_almost_empty : if g_with_wr_almost_empty = TRUE generate
generic map ( U_Sync_AlmostEmpty : gc_sync_ffs
g_sync_edge => "positive") generic map (
port map ( g_sync_edge => "positive")
clk_i => clk_wr_i, port map (
rst_n_i => rst_n_i, clk_i => clk_wr_i,
data_i => almost_empty_int, rst_n_i => rst_n_i,
synced_o => almost_empty_x); data_i => almost_empty_int,
synced_o => almost_empty_x);
end generate gen_with_wr_almost_empty;
rd_almost_empty_o <= almost_empty_int; rd_almost_empty_o <= almost_empty_int;
wr_almost_empty_o <= almost_empty_x; wr_almost_empty_o <= almost_empty_x;
......
modules/genrams/common/inferred_async_fifo_dual_rst.vhd
View file @ 28cd7560
...@@ -114,11 +114,11 @@ architecture arch of inferred_async_fifo_dual_rst is ...@@ -114,11 +114,11 @@ architecture arch of inferred_async_fifo_dual_rst is
signal wr_count, rd_count : t_counter; signal wr_count, rd_count : t_counter;
signal rd_int, we_int : std_logic; signal rd_int, we_int : std_logic;
signal wr_empty_x : std_logic; signal wr_empty_x : std_logic := '0';
signal rd_full_x : std_logic; signal rd_full_x : std_logic := '0';
signal almost_full_x : std_logic; signal almost_full_x : std_logic := '0';
signal almost_empty_x : std_logic; signal almost_empty_x : std_logic := '0';
signal q_int : std_logic_vector(g_data_width-1 downto 0) := (others => '0'); signal q_int : std_logic_vector(g_data_width-1 downto 0) := (others => '0');
...@@ -215,23 +215,28 @@ begin -- arch ...@@ -215,23 +215,28 @@ begin -- arch
end if; end if;
end process p_gen_empty; end process p_gen_empty;
U_Sync_Empty : gc_sync_ffs gen_with_wr_empty : if g_with_wr_empty = TRUE generate
generic map ( U_Sync_Empty : gc_sync_ffs
g_sync_edge => "positive") generic map (
port map ( g_sync_edge => "positive")
clk_i => clk_wr_i, port map (
rst_n_i => '1', clk_i => clk_wr_i,
data_i => empty_int, rst_n_i => '1',
synced_o => wr_empty_x); data_i => empty_int,
synced_o => wr_empty_x);
U_Sync_Full : gc_sync_ffs end generate gen_with_wr_empty;
generic map (
g_sync_edge => "positive")
port map ( gen_with_rd_full : if g_with_rd_full = TRUE generate
clk_i => clk_rd_i, U_Sync_Full : gc_sync_ffs
rst_n_i => '1', generic map (
data_i => full_int, g_sync_edge => "positive")
synced_o => rd_full_x); port map (
clk_i => clk_rd_i,
rst_n_i => '1',
data_i => full_int,
synced_o => rd_full_x);
end generate gen_with_rd_full;
rd_empty_o <= empty_int; rd_empty_o <= empty_int;
wr_empty_o <= wr_empty_x; wr_empty_o <= wr_empty_x;
...@@ -280,14 +285,16 @@ begin -- arch ...@@ -280,14 +285,16 @@ begin -- arch
end if; end if;
end process p_reg_almost_full; end process p_reg_almost_full;
U_Sync_AlmostFull : gc_sync_ffs gen_with_rd_almost_full : if g_with_rd_almost_full = TRUE generate
generic map ( U_Sync_AlmostFull : gc_sync_ffs
g_sync_edge => "positive") generic map (
port map ( g_sync_edge => "positive")
clk_i => clk_rd_i, port map (
rst_n_i => '1', clk_i => clk_rd_i,
data_i => almost_full_int, rst_n_i => '1',
synced_o => almost_full_x); data_i => almost_full_int,
synced_o => almost_full_x);
end generate gen_with_rd_almost_full;
wr_almost_full_o <= almost_full_int; wr_almost_full_o <= almost_full_int;
rd_almost_full_o <= almost_full_x; rd_almost_full_o <= almost_full_x;
...@@ -308,14 +315,16 @@ begin -- arch ...@@ -308,14 +315,16 @@ begin -- arch
end if; end if;
end process p_reg_almost_empty; end process p_reg_almost_empty;
U_Sync_AlmostEmpty : gc_sync_ffs gen_with_wr_almost_empty : if g_with_wr_almost_empty = TRUE generate
generic map ( U_Sync_AlmostEmpty : gc_sync_ffs
g_sync_edge => "positive") generic map (
port map ( g_sync_edge => "positive")
clk_i => clk_wr_i, port map (
rst_n_i => '1', clk_i => clk_wr_i,
data_i => almost_empty_int, rst_n_i => '1',
synced_o => almost_empty_x); data_i => almost_empty_int,
synced_o => almost_empty_x);
end generate gen_with_wr_almost_empty;
rd_almost_empty_o <= almost_empty_int; rd_almost_empty_o <= almost_empty_int;
wr_almost_empty_o <= almost_empty_x; wr_almost_empty_o <= almost_empty_x;
......
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