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Platform-independent core collection
Commits
67d353ad
Commit
67d353ad
authored
May 20, 2019
by
Dimitris Lampridis
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Plain Diff
common: reset cleanup for gc_frequency_meter
parent
66e128d0
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2 changed files
with
19 additions
and
29 deletions
+19
-29
gc_frequency_meter.vhd
modules/common/gc_frequency_meter.vhd
+12
-20
gc_pulse_synchronizer2.vhd
modules/common/gc_pulse_synchronizer2.vhd
+7
-9
No files found.
modules/common/gc_frequency_meter.vhd
View file @
67d353ad
...
...
@@ -39,7 +39,7 @@ entity gc_frequency_meter is
port
(
clk_sys_i
:
in
std_logic
;
clk_in_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- not used, kept for backward compatibility
pps_p1_i
:
in
std_logic
;
freq_o
:
out
std_logic_vector
(
g_counter_bits
-1
downto
0
);
freq_valid_o
:
out
std_logic
...
...
@@ -50,11 +50,11 @@ end gc_frequency_meter;
architecture
behavioral
of
gc_frequency_meter
is
signal
gate_pulse
,
gate_pulse_synced
:
std_logic
;
signal
gate_pulse
,
gate_pulse_synced
:
std_logic
:
=
'0'
;
signal
cntr_gate
:
unsigned
(
g_counter_bits
-1
downto
0
);
signal
cntr_meas
:
unsigned
(
g_counter_bits
-1
downto
0
);
signal
freq_reg
:
std_logic_vector
(
g_counter_bits
-1
downto
0
);
signal
cntr_gate
:
unsigned
(
g_counter_bits
-1
downto
0
)
:
=
(
others
=>
'0'
)
;
signal
cntr_meas
:
unsigned
(
g_counter_bits
-1
downto
0
)
:
=
(
others
=>
'0'
)
;
signal
freq_reg
:
std_logic_vector
(
g_counter_bits
-1
downto
0
)
:
=
(
others
=>
'0'
)
;
begin
...
...
@@ -63,17 +63,12 @@ begin
p_gate_counter
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
if
(
cntr_gate
=
g_clk_sys_freq
-1
)
then
cntr_gate
<=
(
others
=>
'0'
);
gate_pulse
<=
'
0
'
;
gate_pulse
<=
'
1
'
;
else
if
(
cntr_gate
=
g_clk_sys_freq
-1
)
then
cntr_gate
<=
(
others
=>
'0'
);
gate_pulse
<=
'1'
;
else
cntr_gate
<=
cntr_gate
+
1
;
gate_pulse
<=
'0'
;
end
if
;
cntr_gate
<=
cntr_gate
+
1
;
gate_pulse
<=
'0'
;
end
if
;
end
if
;
end
process
;
...
...
@@ -82,7 +77,7 @@ begin
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_in_i
,
rst_n_i
=>
rst_n_i
,
rst_n_i
=>
'1'
,
d_ready_o
=>
freq_valid_o
,
d_p_i
=>
gate_pulse
,
q_p_o
=>
gate_pulse_synced
);
...
...
@@ -95,7 +90,7 @@ begin
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_in_i
,
rst_n_i
=>
rst_n_i
,
rst_n_i
=>
'1'
,
d_ready_o
=>
freq_valid_o
,
d_p_i
=>
pps_p1_i
,
q_p_o
=>
gate_pulse_synced
);
...
...
@@ -105,10 +100,7 @@ begin
p_freq_counter
:
process
(
clk_in_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
-- asynchronous reset (active low)
cntr_meas
<=
(
others
=>
'0'
);
freq_reg
<=
(
others
=>
'0'
);
elsif
rising_edge
(
clk_in_i
)
then
if
rising_edge
(
clk_in_i
)
then
if
(
gate_pulse_synced
=
'1'
)
then
freq_reg
<=
std_logic_vector
(
cntr_meas
);
...
...
modules/common/gc_pulse_synchronizer2.vhd
View file @
67d353ad
...
...
@@ -49,9 +49,11 @@ end gc_pulse_synchronizer2;
architecture
rtl
of
gc_pulse_synchronizer2
is
signal
ready
,
d_p_d0
:
std_logic
;
signal
in_ext
,
out_ext
:
std_logic
;
signal
out_feedback
:
std_logic
;
signal
ready
:
std_logic
:
=
'1'
;
signal
d_p_d0
:
std_logic
:
=
'0'
;
signal
in_ext
:
std_logic
:
=
'0'
;
signal
out_ext
:
std_logic
:
=
'0'
;
signal
out_feedback
:
std_logic
:
=
'0'
;
begin
-- rtl
...
...
@@ -73,13 +75,9 @@ begin -- rtl
npulse_o
=>
open
,
ppulse_o
=>
open
);
p_input_ack
:
process
(
clk_in_i
,
rst_in_n_i
)
p_input_ack
:
process
(
clk_in_i
)
begin
if
rst_in_n_i
=
'0'
then
ready
<=
'1'
;
in_ext
<=
'0'
;
d_p_d0
<=
'0'
;
elsif
rising_edge
(
clk_in_i
)
then
if
rising_edge
(
clk_in_i
)
then
d_p_d0
<=
d_p_i
;
...
...
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