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Commit 044a3bb2 authored by kblantos's avatar kblantos
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Fix the tab spaces in various Testbench files

parent 907c58d0
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testbench/axi/axi4lite32_axi4full64_bridge/tb_axi4lite32_axi4full64_bridge.vhd
View file @ 044a3bb2
......@@ -49,7 +49,7 @@ end entity;
--==============================================================================
architecture tb of tb_axi4lite32_axi4full64_bridge is
--==========================================================
-- constants
--==========================================================
......@@ -63,7 +63,7 @@ architecture tb of tb_axi4lite32_axi4full64_bridge is
--==========================================================
-- Signals
--==========================================================
signal tb_clk_i : std_logic;
signal tb_rst_n_i : std_logic;
-- AXI4-Full slave
......@@ -133,7 +133,7 @@ architecture tb of tb_axi4lite32_axi4full64_bridge is
signal s_wvalid : std_logic;
signal s_arvalid : std_logic;
signal s_rready : std_logic;
signal s_m_awready : std_logic;
signal s_m_awready : std_logic;
signal s_m_wready : std_logic;
signal s_bready : std_logic;
signal s_m_bvalid : std_logic;
......@@ -168,7 +168,7 @@ architecture tb of tb_axi4lite32_axi4full64_bridge is
GenBin(t_wr_state'pos(prev)),
GenBin(t_wr_state'pos(curr)));
end procedure;
-- legal states for Read FSM
procedure fsm_covadd_states_rd (
name : in string;
......@@ -204,7 +204,7 @@ architecture tb of tb_axi4lite32_axi4full64_bridge is
covdb.ICover((t_wr_state'pos(v_state), t_wr_state'pos(state)));
end loop;
end procedure;
-- bin collection for Read FSM
procedure fsm_covcollect_rd (
signal reset : in std_logic;
......@@ -230,7 +230,7 @@ begin
rst_n_i => tb_rst_n_i,
s_awaddr => tb_s_awaddr,
s_awlen => tb_s_awlen,
s_awsize => tb_s_awsize,
s_awsize => tb_s_awsize,
s_awburst => tb_s_awburst,
s_awvalid => tb_s_awvalid,
s_awready => tb_s_awready,
......@@ -239,21 +239,21 @@ begin
s_wlast => tb_s_wlast,
s_wvalid => tb_s_wvalid,
s_wready => tb_s_wready,
s_bresp => tb_s_bresp,
s_bresp => tb_s_bresp,
s_bvalid => tb_s_bvalid,
s_bready => tb_s_bready,
s_araddr => tb_s_araddr,
s_arlen => tb_s_arlen,
s_arsize => tb_s_arsize,
s_arsize => tb_s_arsize,
s_arburst => tb_s_arburst,
s_arvalid => tb_s_arvalid,
s_arready => tb_s_arready,
s_rdata => tb_s_rdata,
s_rdata => tb_s_rdata,
s_rresp => tb_s_rresp,
s_rlast => tb_s_rlast,
s_rvalid => tb_s_rvalid,
s_rready => tb_s_rready,
m_awaddr => tb_m_awaddr,
m_awaddr => tb_m_awaddr,
m_awvalid => tb_m_awvalid,
m_awready => tb_m_awready,
m_wdata => tb_m_wdata,
......@@ -272,16 +272,16 @@ begin
m_rready => tb_m_rready);
-- Clock generation
clk_proc : process
begin
while (not stop) loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
clk_proc : process
begin
while (not stop) loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
-- reset generation
tb_rst_n_i <= '0', '1' after 2*C_CLK_PERIOD;
......@@ -353,7 +353,7 @@ begin
-- de-asserted when reset is low.
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_awready <= '0';
else
......@@ -371,18 +371,18 @@ begin
-- WREADY generation
-- wready is asserted for one clock cycle when both
-- awvalid and wvalid are asserted. wready is
-- de-asserted when reset is low.
-- awvalid and wvalid are asserted. wready is
-- de-asserted when reset is low.
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_wready <= '0';
else
if tb_m_wready = '0' and tb_m_wvalid = '1' and tb_m_awvalid = '1' then
-- slave is ready to accept write data when
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus.
-- on the write address and data bus.
tb_m_wready <= '1';
else
tb_m_wready <= '0';
......@@ -393,40 +393,40 @@ begin
-- RVALID generation
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_rvalid <= '0';
tb_m_rresp <= "00";
else
if tb_m_arready = '1' and tb_m_arvalid = '1' and tb_m_rvalid = '0' then
-- Valid read data is available at the read data bus
tb_m_rvalid <= '1';
tb_m_rresp <= "00"; -- 'OKAY' response
elsif tb_m_rvalid = '1' and tb_m_rready = '1' then
tb_m_rvalid <= '0';
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_rvalid <= '0';
tb_m_rresp <= "00";
else
if tb_m_arready = '1' and tb_m_arvalid = '1' and tb_m_rvalid = '0' then
-- Valid read data is available at the read data bus
tb_m_rvalid <= '1';
tb_m_rresp <= "00"; -- 'OKAY' response
elsif tb_m_rvalid = '1' and tb_m_rready = '1' then
tb_m_rvalid <= '0';
tb_m_rresp <= (others=>'X');
end if;
end if;
end if;
end process;
end if;
end if;
end if;
end process;
-- ARREADY generation
-- ARREADY generation
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_arready <= '0';
else
if tb_m_arready = '0' and tb_m_arvalid = '1' then
-- indicates that the slave has acceped the valid read address
tb_m_arready <= '1';
else
tb_m_arready <= '0';
end if;
end if;
end if;
end process;
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_arready <= '0';
else
if tb_m_arready = '0' and tb_m_arvalid = '1' then
-- indicates that the slave has acceped the valid read address
tb_m_arready <= '1';
else
tb_m_arready <= '0';
end if;
end if;
end if;
end process;
--==============================================================================
-- Coverage --
......@@ -520,10 +520,10 @@ begin
fsm_covadd_illegal("ILLEGAL",sv_cover_wr);
wait;
end process;
-- collect the cov bins
fsm_covcollect_wr(tb_rst_n_i, tb_clk_i, s_wstate, sv_cover_wr);
-- coverage report
cov_report_wr : process
begin
......@@ -611,7 +611,7 @@ begin
fsm_covadd_illegal("ILLEGAL",sv_cover_rd);
wait;
end process;
-- collect the cov bins
fsm_covcollect_rd(tb_rst_n_i, tb_clk_i, s_rstate, sv_cover_rd);
......@@ -639,7 +639,7 @@ begin
report "SLAVE: Wrong WREADY for WVALID LOW" severity error;
end if;
if falling_edge(tb_s_bready) then
assert (tb_s_bvalid = '0')
assert (tb_s_bvalid = '0')
report "SLAVE: Wrong BVALID for BREADY LOW" severity error;
end if;
if falling_edge(tb_s_arvalid) then
......@@ -661,7 +661,7 @@ begin
report "MASTER: Wrong AWVALID for AWREADY LOW" severity error;
end if;
if falling_edge(tb_m_wready) then
assert (tb_m_wvalid = '0')
assert (tb_m_wvalid = '0')
report "MASTER: Wrong WVALID for WREADY LOW" severity error;
end if;
if falling_edge(tb_m_bvalid) then
......@@ -735,7 +735,7 @@ begin
end if;
end if;
end process;
check_m_wdata : process(tb_clk_i)
begin
if rising_edge(tb_clk_i) then
......
testbench/axi/axi4lite_axi4full_bridge/tb_axi4lite_axi4full_bridge.vhd
View file @ 044a3bb2
......@@ -39,7 +39,7 @@ use osvvm.CoveragePkg.all;
-- Entity declaration for tb_axi4lite_axi4full_bridge --
--=============================================================================
entity tb_axi4lite_axi4full_bridge is
entity tb_axi4lite_axi4full_bridge is
generic (
g_seed : natural;
g_ADDR_WIDTH : natural := 32;
......@@ -178,7 +178,7 @@ architecture tb of tb_axi4lite_axi4full_bridge is
GenBin(t_wr_state'pos(prev)),
GenBin(t_wr_state'pos(curr)));
end procedure;
-- legal states for Read FSM
procedure fsm_covadd_states_rd (
name : in string;
......@@ -214,7 +214,7 @@ architecture tb of tb_axi4lite_axi4full_bridge is
covdb.ICover((t_wr_state'pos(v_state), t_wr_state'pos(state)));
end loop;
end procedure;
-- bin collection for Read FSM
procedure fsm_covcollect_rd (
signal reset : in std_logic;
......@@ -418,7 +418,7 @@ begin
-- de-asserted when reset is low.
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_awready <= '0';
else
......@@ -436,18 +436,18 @@ begin
-- WREADY generation
-- wready is asserted for one clock cycle when both
-- awvalid and wvalid are asserted. wready is
-- de-asserted when reset is low.
-- awvalid and wvalid are asserted. wready is
-- de-asserted when reset is low.
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_wready <= '0';
else
if tb_m_wready = '0' and tb_m_wvalid = '1' and tb_m_awvalid = '1' then
-- slave is ready to accept write data when
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus.
-- on the write address and data bus.
tb_m_wready <= '1';
else
tb_m_wready <= '0';
......@@ -458,40 +458,40 @@ begin
-- RVALID generation
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_rvalid <= '0';
tb_m_rresp <= "00";
else
if tb_m_arready = '1' and tb_m_arvalid = '1' and tb_m_rvalid = '0' then
-- Valid read data is available at the read data bus
tb_m_rvalid <= '1';
tb_m_rresp <= "00"; -- 'OKAY' response
elsif tb_m_rvalid = '1' and tb_m_rready = '1' then
tb_m_rvalid <= '0';
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_rvalid <= '0';
tb_m_rresp <= "00";
else
if tb_m_arready = '1' and tb_m_arvalid = '1' and tb_m_rvalid = '0' then
-- Valid read data is available at the read data bus
tb_m_rvalid <= '1';
tb_m_rresp <= "00"; -- 'OKAY' response
elsif tb_m_rvalid = '1' and tb_m_rready = '1' then
tb_m_rvalid <= '0';
tb_m_rresp <= (others=>'X');
end if;
end if;
end if;
end process;
end if;
end if;
end if;
end process;
-- ARREADY generation
-- ARREADY generation
process (tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_arready <= '0';
else
if tb_m_arready = '0' and tb_m_arvalid = '1' then
-- indicates that the slave has acceped the valid read address
tb_m_arready <= '1';
else
tb_m_arready <= '0';
end if;
end if;
end if;
end process;
begin
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
tb_m_arready <= '0';
else
if tb_m_arready = '0' and tb_m_arvalid = '1' then
-- indicates that the slave has acceped the valid read address
tb_m_arready <= '1';
else
tb_m_arready <= '0';
end if;
end if;
end if;
end process;
--==============================================================================
-- Coverage --
......@@ -591,7 +591,7 @@ begin
end if;
end process p_wr_fsm;
-- Legal, illegal states and coverage
-- Legal, illegal states and coverage
-- report for write side FSM
process
begin
......@@ -613,10 +613,10 @@ begin
fsm_covadd_illegal("ILLEGAL",sv_cover_wr);
wait;
end process;
-- collect the cov bins
fsm_covcollect_wr(tb_rst_n_i, tb_clk_i, s_wstate, sv_cover_wr);
-- coverage report
cov_report_wr : process
begin
......@@ -711,7 +711,7 @@ begin
fsm_covadd_illegal("ILLEGAL",sv_cover_rd);
wait;
end process;
-- collect the cov bins
fsm_covcollect_rd(tb_rst_n_i, tb_clk_i, s_rstate, sv_cover_rd);
......@@ -739,7 +739,7 @@ begin
report "SLAVE: Wrong WREADY for WVALID LOW" severity failure;
end if;
if falling_edge(tb_s_bready) then
assert (tb_s_bvalid = '0')
assert (tb_s_bvalid = '0')
report "SLAVE: Wrong BVALID for BREADY LOW" severity failure;
end if;
if falling_edge(tb_s_arvalid) then
......@@ -761,7 +761,7 @@ begin
report "MASTER: Wrong AWVALID for AWREADY LOW" severity failure;
end if;
if falling_edge(tb_m_wready) then
assert (tb_m_wvalid = '0')
assert (tb_m_wvalid = '0')
report "MASTER: Wrong WVALID for WREADY LOW" severity failure;
end if;
if falling_edge(tb_m_bvalid) then
......
testbench/common/gc_delay_line/tb_gc_delay_line.vhd
View file @ 044a3bb2
......@@ -73,7 +73,7 @@ architecture tb of tb_gc_delay_line is
signal stop : boolean;
signal s_cnt : unsigned(g_delay-1 downto 0) := (others=>'0');
-- array used for self-checking
-- array used for self-checking
type t_dly_array is array (0 to g_delay) of std_logic_vector(g_width-1 downto 0);
signal s_dly_arr : t_dly_array;
......@@ -132,7 +132,7 @@ begin
assert (g_delay > 1)
report "Wrong value for Delay" severity failure;
-- Fill in the array with random input data
-- Fill in the array with random input data
delay_array : process(tb_clk_i)
begin
if (tb_rst_n_i = '0') then
......@@ -147,7 +147,7 @@ begin
end if;
end process;
-- Self-checking process
-- Self-checking process
self_check : process(tb_clk_i)
begin
if rising_edge(tb_clk_i) and tb_rst_n_i = '1' then
......
testbench/common/gc_edge_detect/tb_gc_edge_detect.vhd
View file @ 044a3bb2
......@@ -36,80 +36,80 @@ use osvvm.CoveragePkg.all;
entity tb_gc_edge_detect is
generic (
g_seed : natural;
g_ASYNC_RST : boolean := FALSE;
g_PULSE_EDGE : string := "positive";
g_ASYNC_RST : boolean := FALSE;
g_PULSE_EDGE : string := "positive";
g_CLOCK_EDGE : string := "positive");
end entity;
architecture tb of tb_gc_edge_detect is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_i : std_logic;
signal tb_d_i : std_logic := '0';
signal tb_pulse_o : std_logic;
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_i : std_logic;
signal tb_d_i : std_logic := '0';
signal tb_pulse_o : std_logic;
signal stop : boolean;
-- Shared variables, used for coverage
shared variable cp_rst_i : covPType;
begin
-- Unit Under Test
UUT : entity work.gc_edge_detect
generic map (
g_ASYNC_RST => g_ASYNC_RST,
g_PULSE_EDGE => g_PULSE_EDGE,
g_CLOCK_EDGE => g_CLOCK_EDGE)
port map (
clk_i => tb_clk_i,
rst_n_i => tb_rst_i,
data_i => tb_d_i,
pulse_o => tb_pulse_o);
-- Clock generation
clk_proc : process
begin
while STOP = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
-- Reset generation
UUT : entity work.gc_edge_detect
generic map (
g_ASYNC_RST => g_ASYNC_RST,
g_PULSE_EDGE => g_PULSE_EDGE,
g_CLOCK_EDGE => g_CLOCK_EDGE)
port map (
clk_i => tb_clk_i,
rst_n_i => tb_rst_i,
data_i => tb_d_i,
pulse_o => tb_pulse_o);
-- Clock generation
clk_proc : process
begin
while STOP = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
-- Reset generation
tb_rst_i <= '0', '1' after 4*C_CLK_PERIOD;
-- Stimulus
stim : process
variable data : RandomPType;
variable ncycles : natural;
-- Stimulus
stim : process
variable data : RandomPType;
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 4 ms loop
wait until (rising_edge(tb_clk_i) and tb_rst_i = '1');
tb_d_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
while NOW < 4 ms loop
wait until (rising_edge(tb_clk_i) and tb_rst_i = '1');
tb_d_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
report "Test PASS!";
stop <= TRUE;
wait;
end process;
stop <= TRUE;
wait;
end process;
--sets up coverpoint bins
init_coverage : process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
wait;
end process init_coverage;
--sets up coverpoint bins
init_coverage : process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
wait;
end process init_coverage;
--Assertion to check that the width of the output pulse
--is asserted for only one clock cycle
......@@ -124,42 +124,42 @@ begin
end if;
end if;
wait;
end process;
--Assertion to check that output is the same as input
--after one clock cycle
check_output : process
begin
if rising_edge(tb_clk_i) then
if tb_d_i /= tb_pulse_o then
wait for C_CLK_PERIOD;
assert (tb_d_i = tb_pulse_o)
report "Input and Output signals are different"
severity failure;
else
wait for C_CLK_PERIOD;
assert (tb_d_i /= tb_pulse_o)
report "Input and Output signals still the same"
severity failure;
end if;
end if;
wait;
end process check_output;
sample : process
begin
loop
wait on tb_rst_i;
wait for C_CLK_PERIOD;
--sample the coverpoints
cp_rst_i.ICover(to_integer(tb_rst_i = '1'));
end loop;
end process sample;
cover_report: process
begin
wait until stop;
cp_rst_i.writebin;
end process;
end process;
--Assertion to check that output is the same as input
--after one clock cycle
check_output : process
begin
if rising_edge(tb_clk_i) then
if tb_d_i /= tb_pulse_o then
wait for C_CLK_PERIOD;
assert (tb_d_i = tb_pulse_o)
report "Input and Output signals are different"
severity failure;
else
wait for C_CLK_PERIOD;
assert (tb_d_i /= tb_pulse_o)
report "Input and Output signals still the same"
severity failure;
end if;
end if;
wait;
end process check_output;
sample : process
begin
loop
wait on tb_rst_i;
wait for C_CLK_PERIOD;
--sample the coverpoints
cp_rst_i.ICover(to_integer(tb_rst_i = '1'));
end loop;
end process sample;
cover_report: process
begin
wait until stop;
cp_rst_i.writebin;
end process;
end tb;
testbench/common/gc_frequency_meter/tb_gc_frequency_meter.vhd
View file @ 044a3bb2
......@@ -53,7 +53,7 @@ entity tb_gc_frequency_meter is
generic (
g_seed : natural;
g_WITH_INTERNAL_TIMEBASE : boolean := FALSE;
g_CLK_SYS_FREQ : integer := 10;
g_CLK_SYS_FREQ : integer := 10;
g_SYNC_OUT : boolean := FALSE;
g_COUNTER_BITS : integer := 8);
end entity;
......@@ -67,7 +67,7 @@ architecture tb of tb_gc_frequency_meter is
-- Signals
signal tb_clk_sys_i : std_logic;
signal tb_clk_in_i : std_logic;
signal tb_rst_n_i : std_logic;
signal tb_rst_n_i : std_logic;
signal tb_pps_p1_i : std_logic;
signal tb_freq_o : std_logic_vector(g_COUNTER_BITS-1 downto 0);
signal tb_freq_valid_o : std_logic;
......@@ -97,16 +97,16 @@ begin
freq_valid_o => tb_freq_valid_o);
-- Clocks generation
clk_sys_proc : process
begin
while not stop loop
tb_clk_sys_i <= '1';
wait for C_CLK_SYS_PERIOD/2;
tb_clk_sys_i <= '0';
wait for C_CLK_SYS_PERIOD/2;
end loop;
wait;
end process clk_sys_proc;
clk_sys_proc : process
begin
while not stop loop
tb_clk_sys_i <= '1';
wait for C_CLK_SYS_PERIOD/2;
tb_clk_sys_i <= '0';
wait for C_CLK_SYS_PERIOD/2;
end loop;
wait;
end process clk_sys_proc;
clk_in_proc : process
begin
......@@ -119,62 +119,62 @@ begin
wait;
end process clk_in_proc;
-- Reset generation
-- Reset generation
tb_rst_n_i <= '0', '1' after 4*C_CLK_SYS_PERIOD;
-- Stimulus if g_with_internal_timebase = TRUE
stim_with_internal_timebase : if (g_with_internal_timebase = TRUE) generate
stim : process
variable ncycles : natural;
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 2 ms loop
while NOW < 2 ms loop
wait until rising_edge(tb_clk_sys_i);
tb_pps_p1_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
tb_pps_p1_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
end generate;
-- Stimulus if g_with_internal_timebase = TRUE
stim_without_internal_timebase : if (g_with_internal_timebase = FALSE) generate
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
variable data : RandomPType;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 2 ms loop
wait until (rising_edge(tb_clk_sys_i) and tb_freq_valid_o = '1');
tb_pps_p1_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
while NOW < 2 ms loop
wait until (rising_edge(tb_clk_sys_i) and tb_freq_valid_o = '1');
tb_pps_p1_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
end generate;
--------------------------------------------------------------------------------
-- Self-Checking and Assertions
--------------------------------------------------------------------------------
-- Reproduce the behavior of the internal counter
with_internal_timebase : if (g_WITH_INTERNAL_TIMEBASE = TRUE) generate
internal_counter : process(tb_clk_sys_i)
begin
if rising_edge(tb_clk_sys_i) then
if s_cnt_gate = g_CLK_SYS_FREQ-1 then
s_cnt_gate <= (others=>'0');
s_gate_pulse <= '1';
s_gate_pulse <= '1';
else
s_cnt_gate <= s_cnt_gate + 1;
s_gate_pulse <= '0';
......@@ -194,12 +194,12 @@ begin
s_gate_pulse_synced <= '0';
end loop;
end process;
end generate with_internal_timebase;
-- Reproduce the behavior when no internal timebase activated
no_internal_timebase : if (g_WITH_INTERNAL_TIMEBASE = FALSE) generate
no_internal_timebase : if (g_WITH_INTERNAL_TIMEBASE = FALSE) generate
no_internal_counter : process
begin
while not stop loop
......@@ -228,7 +228,7 @@ begin
end if;
end process;
sync_out : if (g_SYNC_OUT = FALSE) generate
sync_out : if (g_SYNC_OUT = FALSE) generate
check_unsync_out_data : process
begin
while not stop loop
......@@ -252,7 +252,7 @@ begin
assert (s_data_o = s_freq)
report "Data mismatch" severity failure;
end loop;
end process;
end process;
end generate;
end tb;
testbench/common/gc_multichannel_frequency_meter/tb_gc_multichannel_frequency_meter.vhd
View file @ 044a3bb2
......@@ -64,22 +64,22 @@ architecture tb of tb_gc_multichannel_frequency_meter is
signal s_gate_pulse_synced : std_logic_vector(g_CHANNELS-1 downto 0) := (others=>'0');
signal s_data_o : std_logic_vector(g_COUNTER_BITS-1 downto 0) := (others=>'0');
signal s_freq_valid_o : std_logic:='0';
-- Types
type t_channel is record
cnt : unsigned(g_COUNTER_BITS-1 downto 0);
freq : unsigned(g_COUNTER_BITS-1 downto 0);
freq_valid_o: std_logic;
end record;
type t_channel_array is array (0 to g_CHANNELS-1) of t_channel;
signal ch : t_channel_array;
signal index : integer range 0 to g_CHANNELS+1;
signal index : integer range 0 to g_CHANNELS+1;
signal s_ready_o : std_logic := '0';
begin
-- Unit Under Test
-- Unit Under Test
UUT : entity work.gc_multichannel_frequency_meter
generic map (
g_WITH_INTERNAL_TIMEBASE => g_WITH_INTERNAL_TIMEBASE,
......@@ -88,31 +88,31 @@ begin
g_CHANNELS => g_CHANNELS)
port map (
clk_sys_i => tb_clk_sys_i,
clk_in_i => tb_clk_in_i,
clk_in_i => tb_clk_in_i,
rst_n_i => tb_rst_n_i,
pps_p1_i => tb_pps_p1_i,
channel_sel_i => tb_channel_sel_i,
freq_o => tb_freq_o,
channel_sel_i => tb_channel_sel_i,
freq_o => tb_freq_o,
freq_valid_o => tb_freq_valid_o);
-- Clock generation
clk_sys_proc : process
begin
while STOP = FALSE loop
tb_clk_sys_i <= '1';
wait for C_CLK_SYS_PERIOD/2;
tb_clk_sys_i <= '0';
wait for C_CLK_SYS_PERIOD/2;
end loop;
wait;
end process clk_sys_proc;
-- Reset generation
clk_sys_proc : process
begin
while STOP = FALSE loop
tb_clk_sys_i <= '1';
wait for C_CLK_SYS_PERIOD/2;
tb_clk_sys_i <= '0';
wait for C_CLK_SYS_PERIOD/2;
end loop;
wait;
end process clk_sys_proc;
-- Reset generation
tb_rst_n_i <= '0', '1' after 4*C_CLK_SYS_PERIOD;
-- Stimulus
-- Stimulus
stim : process
variable ncycles : natural;
variable ncycles : natural;
variable data : RandomPType;
begin
data.InitSeed(g_seed);
......@@ -121,49 +121,49 @@ begin
tb_clk_in_i <= data.randSlv(g_CHANNELS);
wait until (rising_edge(tb_clk_sys_i) and tb_rst_n_i = '1');
tb_channel_sel_i <= data.randslv(0,g_CHANNELS-1,f_log2_ceil(g_CHANNELS));
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
-- Stimulus for pps_p1_i when time internal is FALSE
stim_when_false : if (g_WITH_INTERNAL_TIMEBASE = FALSE) generate
stim_false : process
variable data : RandomPType;
variable data : RandomPType;
begin
data.InitSeed(g_seed);
while NOW < 2 ms loop
while NOW < 2 ms loop
wait until rising_edge(tb_clk_sys_i) and s_ready_o='1';
tb_pps_p1_i <= data.randSlv(1)(1);
end loop;
wait;
end process;
tb_pps_p1_i <= data.randSlv(1)(1);
end loop;
wait;
end process;
end generate;
-- Stimulus for pps_p1_i when time internal is TRUE
stim_when_true : if (g_WITH_INTERNAL_TIMEBASE = TRUE) generate
stim_false : process
variable data : RandomPType;
variable data : RandomPType;
begin
data.InitSeed(g_seed);
while NOW < 2 ms loop
while NOW < 2 ms loop
wait until (rising_edge(tb_clk_sys_i) and tb_rst_n_i='1');
tb_pps_p1_i <= data.randSlv(1)(1);
end loop;
wait;
end process;
tb_pps_p1_i <= data.randSlv(1)(1);
end loop;
wait;
end process;
end generate;
--------------------------------------------------------------------------------
-- Self-Checking and Assertions --
--------------------------------------------------------------------------------
-- Reproduce the behavior of the internal counter
with_internal_timebase : if (g_WITH_INTERNAL_TIMEBASE = TRUE) generate
internal_counter : process(tb_clk_sys_i)
begin
if rising_edge(tb_clk_sys_i) then
......@@ -173,7 +173,7 @@ begin
else
if s_cnt_gate = g_CLK_SYS_FREQ-1 then
s_cnt_gate <= (others=>'0');
s_gate_pulse <= '1';
s_gate_pulse <= '1';
else
s_cnt_gate <= s_cnt_gate + 1;
s_gate_pulse <= '0';
......@@ -184,7 +184,7 @@ begin
end generate with_internal_timebase;
-- Reproduce the RTL behavarior to generate self-check
-- Reproduce the RTL behavarior to generate self-check
gen_channels : for i in 0 to g_CHANNELS-1 generate
internal_timebase : if (g_WITH_INTERNAL_TIMEBASE=TRUE) generate
......@@ -208,7 +208,7 @@ begin
clk_in_i => tb_clk_sys_i,
clk_out_i => tb_clk_in_i(i),
rst_n_i => tb_rst_n_i,
d_ready_o => s_ready_o,
d_ready_o => s_ready_o,
d_p_i => tb_pps_p1_i,
q_p_o => s_gate_pulse_synced(i));
......
testbench/common/gc_negedge/tb_gc_negedge.vhd
View file @ 044a3bb2
......@@ -44,8 +44,8 @@ architecture tb of tb_gc_negedge is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_n_i : std_logic;
signal tb_data_i : std_logic := '0';
......@@ -71,43 +71,43 @@ begin
pulse_o => tb_pulse_o);
-- Clock generation
clk_proc : process
begin
clk_proc : process
begin
while STOP = FALSE loop
tb_clk_i <= '1';
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
end loop;
wait;
end process clk_proc;
-- Reset generation
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
-- Stimulus
stim : process
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
wait until tb_rst_n_i='1';
while NOW < 4 ms loop
while NOW < 4 ms loop
wait until rising_edge(tb_clk_i);
tb_data_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
-- Assertion to check that the width of the output pulse
-- is asserted for only one clock cycle
one_clk_width : process
......@@ -124,14 +124,14 @@ begin
wait;
end process;
-- Check that the output pulse is asserted
-- Check that the output pulse is asserted
-- in the falling edge of the input pulse
check_negedge : process
begin
while not stop loop
wait until falling_edge(tb_data_i);
wait for 0 ns; --wait for delta time
assert (tb_pulse_o='1')
assert (tb_pulse_o='1')
report "Negative edge didn't detect" severity failure;
end loop;
wait;
......@@ -142,23 +142,23 @@ begin
--------------------------------------------------------------------------------
--sets up coverpoint bins
init_coverage : process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
init_coverage : process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
cp_data_i.AddBins("Input pulse detected", ONE_BIN);
cp_pulse_o.AddBins("Output pulse detected", ONE_BIN);
wait;
end process init_coverage;
wait;
end process init_coverage;
-- sample coverpoints for reset
sample_rst_n_i : process
begin
loop
wait on tb_rst_n_i;
wait for C_CLK_PERIOD;
cp_rst_i.ICover(to_integer(tb_rst_n_i = '1'));
end loop;
end process;
begin
loop
wait on tb_rst_n_i;
wait for C_CLK_PERIOD;
cp_rst_i.ICover(to_integer(tb_rst_n_i = '1'));
end loop;
end process;
-- sample coverpoints for input data
sample_data_i : process(tb_clk_i)
......@@ -189,15 +189,15 @@ begin
end process;
end generate;
-- Coverage report
-- Coverage report
cover_report: process
begin
wait until stop;
cp_rst_i.writebin;
begin
wait until stop;
cp_rst_i.writebin;
cp_data_i.writebin;
cp_pulse_o.writebin;
report "PASS";
end process;
report "PASS";
end process;
......
testbench/common/gc_posedge/tb_gc_posedge.vhd
View file @ 044a3bb2
......@@ -44,14 +44,14 @@ architecture tb of tb_gc_posedge is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_n_i : std_logic;
signal tb_data_i : std_logic := '0';
signal tb_pulse_o : std_logic;
signal stop : boolean;
-- Variables used for coverage
shared variable cp_rst_i : covPType;
shared variable cp_data_i : covPType;
......@@ -71,43 +71,43 @@ begin
pulse_o => tb_pulse_o);
-- Clock generation
clk_proc : process
begin
clk_proc : process
begin
while STOP = FALSE loop
tb_clk_i <= '1';
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
end loop;
wait;
end process clk_proc;
-- Reset generation
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
-- Stimulus
stim : process
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
wait until tb_rst_n_i='1';
while NOW < 2 ms loop
while NOW < 2 ms loop
wait until rising_edge(tb_clk_i);
tb_data_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
--Assertion to check that the width of the output pulse
--is asserted for only one clock cycle
one_clk_width : process
......@@ -124,14 +124,14 @@ begin
wait;
end process;
-- Check that the output pulse is asserted
-- Check that the output pulse is asserted
-- in the rising edge of the input pulse
check_edge : process
begin
while not stop loop
wait until rising_edge(tb_data_i);
wait for 0 ns; --wait for delta time
assert (tb_pulse_o = '1')
assert (tb_pulse_o = '1')
report "Positive edge didn't detect"
severity failure;
end loop;
......@@ -143,23 +143,23 @@ begin
--------------------------------------------------------------------------------
--sets up coverpoint bins
init_coverage : process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
init_coverage : process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
cp_data_i.AddBins("Input pulse detected", ONE_BIN);
cp_pulse_o.AddBins("Output pulse detected", ONE_BIN);
wait;
end process init_coverage;
wait;
end process init_coverage;
-- sample coverpoints for reset
sample_rst_n_i : process
begin
begin
loop
wait on tb_rst_n_i;
wait for C_CLK_PERIOD;
cp_rst_i.ICover(to_integer(tb_rst_n_i = '1'));
end loop;
end process;
end process;
-- sample coverpoints for input data
sample_data_i : process(tb_clk_i)
......@@ -190,13 +190,13 @@ begin
end process;
end generate;
-- Coverage report
-- Coverage report
cover_report: process
begin
wait until stop;
cp_rst_i.writebin;
begin
wait until stop;
cp_rst_i.writebin;
cp_data_i.writebin;
cp_pulse_o.writebin;
end process;
end process;
end tb;
testbench/common/gc_prio_encoder/tb_gc_prio_encoder.vhd
View file @ 044a3bb2
......@@ -75,12 +75,12 @@ architecture tb of tb_gc_prio_encoder is
type t_stages_array is array (0 to C_STAGES) of std_logic_vector(g_width-1 downto 0);
signal s_stage : t_stages_array;
signal s_data_o : std_logic_vector(g_width-1 downto 0);
signal s_data_o : std_logic_vector(g_width-1 downto 0);
begin
-- Unit Under Test
UUT : entity work.gc_prio_encoder
UUT : entity work.gc_prio_encoder
generic map (
g_width => g_width)
port map (
......@@ -88,22 +88,22 @@ begin
therm_o => tb_therm_o);
-- Stimulus
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 2 ms loop
while NOW < 2 ms loop
wait for 10 ns; --give every 10ns a new input
tb_d_i <= data.randSlv(g_width);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
tb_d_i <= data.randSlv(g_width);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
--------------------------------------------------------------------------------
-- Reproduce the RTL behavior in order to compare it with the actual RTL
......@@ -112,17 +112,17 @@ begin
nof_stages : for i in 1 to C_STAGES generate
data_width : for j in 0 to g_width-1 generate
case_1 : if (j mod (2 ** i) >= (2 ** (i-1))) generate
s_stage(i)(j) <= s_stage(i-1)(j) or s_stage(i-1) (j - (j mod (2**i)) + (2**(i-1)) - 1);
end generate;
case_2 : if not (j mod (2 ** i) >= (2 ** (i-1))) generate
s_stage(i)(j) <= s_stage(i-1)(j);
end generate;
end generate;
end generate;
s_data_o <= s_stage(C_STAGES);
--------------------------------------------------------------------------------
......
testbench/common/gc_pulse_synchronizer/tb_gc_pulse_synchronizer.vhd
View file @ 044a3bb2
......@@ -6,7 +6,7 @@
--
-- unit name: tb_gc_pulse_synchronizer
--
-- description: testbench for full feedback pulse synchronizer (works
-- description: testbench for full feedback pulse synchronizer (works
-- independently of the input/output clock domain frequency ratio)
--
--------------------------------------------------------------------------------
......@@ -43,8 +43,8 @@ architecture tb of tb_gc_pulse_synchronizer is
constant C_CLK_IN_PERIOD : time := 10 ns;
constant C_CLK_OUT_PERIOD : time := 8 ns;
--signals
signal tb_clk_in_i : std_logic;
--signals
signal tb_clk_in_i : std_logic;
signal tb_rst_n_i : std_logic;
signal tb_clk_out_i : std_logic;
signal tb_d_ready_o : std_logic;
......@@ -54,25 +54,25 @@ architecture tb of tb_gc_pulse_synchronizer is
-- Shared variables used for coverage
shared variable cp_rst_in_i : covPType;
shared variable cp_data_i : covPType;
shared variable cp_data_o : covPType;
shared variable cp_data_o : covPType;
signal stop : boolean := FALSE;
signal stop : boolean := FALSE;
begin
-- Unit Under Test
UUT : entity work.gc_pulse_synchronizer
port map (
clk_in_i => tb_clk_in_i,
port map (
clk_in_i => tb_clk_in_i,
rst_n_i => tb_rst_n_i,
clk_out_i => tb_clk_out_i,
d_ready_o => tb_d_ready_o,
d_p_i => tb_d_p_i,
q_p_o => tb_q_p_o);
--clocks generation
clk_in_gen : process
begin
clk_in_gen : process
begin
while not stop loop
tb_clk_in_i <= '1';
wait for C_CLK_IN_PERIOD/2;
......@@ -80,10 +80,10 @@ begin
wait for C_CLK_IN_PERIOD/2;
end loop;
wait;
end process;
end process;
clk_out_gen : process
begin
clk_out_gen : process
begin
while not stop loop
tb_clk_out_i <= '1';
wait for C_CLK_OUT_PERIOD/2;
......@@ -91,7 +91,7 @@ begin
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
end process;
end process;
-- Reset generation
tb_rst_n_i <= '0', '1' after 2*C_CLK_IN_PERIOD;
......@@ -115,11 +115,11 @@ begin
end process;
--------------------------------------------------------------------------------
-- Assertions --
-- Assertions --
--------------------------------------------------------------------------------
-- Self-Checking : after the de-assertion of ready_o, in the next rising edge
-- of clock we expect the output to be HIGH
-- of clock we expect the output to be HIGH
valid_out_data : process
begin
while not stop loop
......@@ -138,23 +138,23 @@ begin
--------------------------------------------------------------------------------
--sets up coverpoint bins
init_coverage : process
begin
cp_rst_in_i.AddBins("reset in has been asserted", ONE_BIN);
init_coverage : process
begin
cp_rst_in_i.AddBins("reset in has been asserted", ONE_BIN);
cp_data_i.AddBins("new HIGH data arrived", ONE_BIN);
cp_data_o.AddBins("output pulse for HIGH input", ONE_BIN);
wait;
end process init_coverage;
wait;
end process init_coverage;
-- Sample the coverpoints
sample_rst_i : process
begin
loop
wait on tb_rst_n_i;
wait for C_CLK_IN_PERIOD;
cp_rst_in_i.ICover(to_integer(tb_rst_n_i = '1'));
end loop;
end process sample_rst_i;
sample_rst_i : process
begin
loop
wait on tb_rst_n_i;
wait for C_CLK_IN_PERIOD;
cp_rst_in_i.ICover(to_integer(tb_rst_n_i = '1'));
end loop;
end process sample_rst_i;
sample_data_i : process
begin
......@@ -174,13 +174,13 @@ begin
end loop;
end process;
cover_report: process
begin
wait until stop;
cp_rst_in_i.writebin;
cover_report: process
begin
wait until stop;
cp_rst_in_i.writebin;
cp_data_i.writebin;
cp_data_o.writebin;
end process;
end process;
end tb;
......
testbench/common/gc_pulse_synchronizer2/tb_gc_pulse_synchronizer2.vhd
View file @ 044a3bb2
......@@ -46,8 +46,8 @@ architecture tb of tb_gc_pulse_synchronizer2 is
constant C_CLK_IN_PERIOD : time := 5 ns;
constant C_CLK_OUT_PERIOD : time := 10 ns;
-- signals
signal tb_clk_in_i : std_logic;
-- signals
signal tb_clk_in_i : std_logic;
signal tb_rst_in_n_i : std_logic;
signal tb_clk_out_i : std_logic;
signal tb_rst_out_n_i : std_logic;
......@@ -55,31 +55,31 @@ architecture tb of tb_gc_pulse_synchronizer2 is
signal tb_d_ack_p_o : std_logic;
signal tb_d_p_i : std_logic := '0';
signal tb_q_p_o : std_logic;
signal stop : boolean := FALSE;
signal stop : boolean := FALSE;
-- Shared variables used for coverage
shared variable cp_rst_in_i : covPType;
shared variable cp_rst_in_i : covPType;
shared variable cp_rst_out_i : covPType;
shared variable cp_data_i : covPType;
shared variable cp_data_o : covPType;
begin
-- Unit Under Test
UUT : entity work.gc_pulse_synchronizer2
port map (
clk_in_i => tb_clk_in_i,
rst_in_n_i => tb_rst_in_n_i,
clk_out_i => tb_clk_out_i,
rst_out_n_i => tb_rst_out_n_i,
d_ready_o => tb_d_ready_o,
d_ack_p_o => tb_d_ack_p_o,
d_p_i => tb_d_p_i,
q_p_o => tb_q_p_o);
-- Clocks generation
clk_in_gen : process
begin
-- Unit Under Test
UUT : entity work.gc_pulse_synchronizer2
port map (
clk_in_i => tb_clk_in_i,
rst_in_n_i => tb_rst_in_n_i,
clk_out_i => tb_clk_out_i,
rst_out_n_i => tb_rst_out_n_i,
d_ready_o => tb_d_ready_o,
d_ack_p_o => tb_d_ack_p_o,
d_p_i => tb_d_p_i,
q_p_o => tb_q_p_o);
-- Clocks generation
clk_in_gen : process
begin
while not stop loop
tb_clk_in_i <= '1';
wait for C_CLK_IN_PERIOD/2;
......@@ -87,10 +87,10 @@ begin
wait for C_CLK_IN_PERIOD/2;
end loop;
wait;
end process;
end process;
clk_out_gen : process
begin
clk_out_gen : process
begin
while not stop loop
tb_clk_out_i <= '1';
wait for C_CLK_OUT_PERIOD/2;
......@@ -98,11 +98,11 @@ begin
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
end process;
end process;
-- Resets generation
tb_rst_in_n_i <= '0', '1' after 2*C_CLK_IN_PERIOD;
tb_rst_out_n_i <= '0', '1' after 2*C_CLK_OUT_PERIOD;
tb_rst_in_n_i <= '0', '1' after 2*C_CLK_IN_PERIOD;
tb_rst_out_n_i <= '0', '1' after 2*C_CLK_OUT_PERIOD;
-- Stimulus
......@@ -127,7 +127,7 @@ begin
-- Assertions --
--------------------------------------------------------------------------------
-- Self-Checking : after the de-assertion of ready_o, after one clock cycle
-- Self-Checking : after the de-assertion of ready_o, after one clock cycle
-- (due to g_sync module), we want the output to be like the input pulse
-- but last for one clock
valid_out_data : process
......@@ -145,36 +145,36 @@ begin
--------------------------------------------------------------------------------
-- Coverage --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--sets up coverpoint bins
init_coverage : process
begin
cp_rst_in_i.AddBins("reset in has been asserted", ONE_BIN);
init_coverage : process
begin
cp_rst_in_i.AddBins("reset in has been asserted", ONE_BIN);
cp_rst_out_i.AddBins("reset out has been asserted",ONE_BIN);
cp_data_i.AddBins("new HIGH data arrives",ONE_BIN);
cp_data_o.AddBins("output pulse for HIGH input",ONE_BIN);
wait;
end process init_coverage;
wait;
end process init_coverage;
-- Sample the coverpoints
sample_rst_i : process
begin
loop
wait on tb_rst_in_n_i;
wait for C_CLK_IN_PERIOD;
cp_rst_in_i.ICover(to_integer(tb_rst_in_n_i = '1'));
end loop;
end process sample_rst_i;
sample_rst_out : process
begin
loop
wait on tb_rst_out_n_i;
wait for C_CLK_OUT_PERIOD;
cp_rst_out_i.ICover(to_integer(tb_rst_out_n_i = '1'));
end loop;
end process sample_rst_out;
sample_rst_i : process
begin
loop
wait on tb_rst_in_n_i;
wait for C_CLK_IN_PERIOD;
cp_rst_in_i.ICover(to_integer(tb_rst_in_n_i = '1'));
end loop;
end process sample_rst_i;
sample_rst_out : process
begin
loop
wait on tb_rst_out_n_i;
wait for C_CLK_OUT_PERIOD;
cp_rst_out_i.ICover(to_integer(tb_rst_out_n_i = '1'));
end loop;
end process sample_rst_out;
sample_data_i : process
begin
......@@ -195,14 +195,14 @@ begin
end process;
-- coverage reports
cover_report: process
begin
wait until stop;
cp_rst_out_i.writebin;
cp_rst_in_i.writebin;
cover_report: process
begin
wait until stop;
cp_rst_out_i.writebin;
cp_rst_in_i.writebin;
cp_data_i.writebin;
cp_data_o.writebin;
end process;
end process;
......
testbench/common/gc_reset/tb_gc_reset.vhd
View file @ 044a3bb2
......@@ -80,16 +80,16 @@ begin
rstn_o => tb_rstn_o);
-- Clock generation
clk_proc : process
begin
clk_proc : process
begin
while not stop loop
tb_free_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_free_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
wait;
end process clk_proc;
-- Stimulus
stim : process
......@@ -100,14 +100,14 @@ begin
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 8 ms loop
wait until (rising_edge(tb_free_clk_i));
tb_locked_i <= data.randSlv(1)(1);
tb_locked_i <= data.randSlv(1)(1);
tb_clks_i <= data.randSlv(g_clocks);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
wait;
end process stim;
--------------------------------------------------------------------------------
......@@ -141,7 +141,7 @@ begin
end if;
end process;
s_rstn_o(i) <= s_sync_chains(i)(0);
end generate;
end generate;
--------------------------------------------------------------------------------
-- Assertions --
......@@ -153,28 +153,28 @@ begin
assert (tb_rstn_o = s_rstn_o)
report "Output mimatch" severity failure;
end if;
end process;
end process;
--------------------------------------------------------------------------------
-- Coverage --
--------------------------------------------------------------------------------
--sets up coverpoint bins
init_coverage : process
begin
init_coverage : process
begin
cp_master_rstn.AddBins("Master reset asserted", ONE_BIN);
cp_rstn_o.AddBins("Output reset asserted", ONE_BIN);
wait;
end process init_coverage;
wait;
end process init_coverage;
-- sample coverpoints for reset
sample_rst_n_i : process
begin
loop
wait until (rising_edge(tb_free_clk_i));
cp_master_rstn.ICover(to_integer(s_master_rstn = '1'));
end loop;
end process;
begin
loop
wait until (rising_edge(tb_free_clk_i));
cp_master_rstn.ICover(to_integer(s_master_rstn = '1'));
end loop;
end process;
-- sample coverpoints for input data
sample_rstn_o : process(tb_free_clk_i)
......@@ -186,12 +186,12 @@ begin
end loop;
end process;
-- Coverage report
-- Coverage report
cover_report: process
begin
wait until stop;
begin
wait until stop;
cp_master_rstn.writebin;
cp_rstn_o.writebin;
end process;
end process;
end tb;
testbench/common/gc_reset_multi_aasd/tb_gc_reset_multi_aasd.vhd
View file @ 044a3bb2
......@@ -8,9 +8,9 @@
--
-- unit name: tb_gc_reset_multi_aasd
--
-- description: Testbench for multiple clock domain reset generator and
-- synchronizer with Asynchronous Assert and
-- Syncrhonous Deassert (AASD).
-- description: Testbench for multiple clock domain reset generator and
-- synchronizer with Asynchronous Assert and
-- Syncrhonous Deassert (AASD).
--
--------------------------------------------------------------------------------
-- Copyright CERN 2018
......@@ -38,22 +38,22 @@ use osvvm.CoveragePkg.all;
entity tb_gc_reset_multi_aasd is
generic (
g_seed : natural;
-- number of clock domains
g_CLOCKS : natural := 2;
-- number of clock domains
g_CLOCKS : natural := 2;
-- Number of clock ticks (per domain) that the input reset must remain
-- deasserted and stable before deasserting the reset output(s)
g_RST_LEN : natural := 1);
g_RST_LEN : natural := 1);
end entity;
architecture tb of tb_gc_reset_multi_aasd is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
signal tb_arst_i : std_logic := '0';
signal tb_clks_i : std_logic_vector(g_CLOCKS-1 downto 0) := (others=>'0');
signal tb_rst_n_o : std_logic_vector(g_CLOCKS-1 downto 0);
-- Signals
signal tb_arst_i : std_logic := '0';
signal tb_clks_i : std_logic_vector(g_CLOCKS-1 downto 0) := (others=>'0');
signal tb_rst_n_o : std_logic_vector(g_CLOCKS-1 downto 0);
signal stop : boolean;
signal s_cnt_rst : unsigned(g_RST_LEN-1 downto 0) := (others=>'0');
signal s_cnt_clks : unsigned(g_CLOCKS-1 downto 0) := (others=>'0');
......@@ -65,35 +65,35 @@ architecture tb of tb_gc_reset_multi_aasd is
begin
--Unit Under Test
UUT : entity work.gc_reset_multi_aasd
generic map (
g_CLOCKS => g_CLOCKS,
g_RST_LEN => g_RST_LEN)
port map (
arst_i => tb_arst_i,
clks_i => tb_clks_i,
rst_n_o => tb_rst_n_o);
--Stimulus
stim : process
variable ncycles : natural;
--Unit Under Test
UUT : entity work.gc_reset_multi_aasd
generic map (
g_CLOCKS => g_CLOCKS,
g_RST_LEN => g_RST_LEN)
port map (
arst_i => tb_arst_i,
clks_i => tb_clks_i,
rst_n_o => tb_rst_n_o);
--Stimulus
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 1 ms loop
wait for C_CLK_PERIOD;
tb_clks_i <= data.randSlv(g_CLOCKS);
tb_arst_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
tb_clks_i <= data.randSlv(g_CLOCKS);
tb_arst_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
end process;
wait;
end process;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
......@@ -105,7 +105,7 @@ begin
-- Assertion 2: for one clock domain
single_clk_domain : if (g_CLOCKS = 1) generate
assert_check : for I in g_CLOCKS-1 downto 0 generate
assert_check : for I in g_CLOCKS-1 downto 0 generate
check : process(tb_clks_i, tb_arst_i)
begin
if tb_arst_i = '0' then
......@@ -117,7 +117,7 @@ begin
report "wrong" severity failure;
end if;
end if;
else
else
s_cnt_rst <= (others=>'0');
end if;
end process;
......@@ -129,16 +129,16 @@ begin
-- Assertion 3: for many clock domains
many_clk_domains : if (g_CLOCKS > 1) generate
assert_check : for I in g_CLOCKS-1 downto 0 generate
check : process(tb_clks_i, s_rst)
begin
if s_rst = '1' then --if NOT reset
s_rst_chains(i) <= (others=>'0');
elsif rising_edge(tb_clks_i(i)) then
elsif rising_edge(tb_clks_i(i)) then
s_rst_chains(i) <= '1' & s_rst_chains(i)(g_RST_LEN-1 downto 1);
end if;
end process;
process(tb_clks_i, s_rst)
begin
if s_rst = '0' then
......@@ -150,6 +150,6 @@ begin
end process;
end generate;
end generate;
end generate;
end tb;
testbench/common/gc_serial_dac/tb_gc_serial_dac.vhd
View file @ 044a3bb2
......@@ -6,13 +6,13 @@
-- Author : Konstantinos Blantos
-- Company : CERN BE-CEM-EDL
-- Created : 2021-12-17
-- Last update:
-- Last update:
-- Platform : FPGA-generic
-- Standard : VHDL 2008
-------------------------------------------------------------------------------
-- Description: Testbench for the DAC unit provides an interface to a 16 bit
-- serial Digital to Analogue converter (MAX5441, AD5662, SPI/QSPI/MICROWIRE
-- compatible)
-- Description: Testbench for the DAC unit provides an interface to a 16 bit
-- serial Digital to Analogue converter (MAX5441, AD5662, SPI/QSPI/MICROWIRE
-- compatible)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
......@@ -42,7 +42,7 @@ use osvvm.CoveragePkg.all;
entity tb_gc_serial_dac is
generic (
g_seed : natural;
g_num_data_bits : integer := 2;
g_num_data_bits : integer := 2;
g_num_extra_bits : integer := 0;
g_num_cs_select : integer := 1;
g_sclk_polarity : integer := 0);
......@@ -65,7 +65,7 @@ architecture tb of tb_gc_serial_dac is
signal tb_dac_sdata_o : std_logic;
signal tb_busy_o : std_logic;
signal stop : boolean;
signal s_data_o : std_logic_vector(g_num_data_bits+g_num_extra_bits-1 downto 0);
signal s_data_o : std_logic_vector(g_num_data_bits+g_num_extra_bits-1 downto 0);
signal s_divider : unsigned(11 downto 0);
signal s_div_muxed : std_logic;
signal s_bit_cnt : std_logic_vector(g_num_data_bits+g_num_extra_bits+1 downto 0);
......@@ -98,16 +98,16 @@ begin
busy_o => tb_busy_o);
-- Clock generation
clk_proc : process
begin
clk_proc : process
begin
while not stop loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
-- Reset generation
tb_rst_n_i <= '0', '1' after 2*C_CLK_PERIOD;
......@@ -115,21 +115,21 @@ begin
-- Stimulus
stim : process
variable data : RandomPType;
variable ncycles : natural;
variable ncycles : natural;
begin
while NOW < 4 ms loop
-- when we are not busy, we sent data
wait until (rising_edge(tb_clk_i) and tb_busy_o = '0');
tb_value_i <= data.randSlv(g_num_data_bits);
tb_value_i <= data.randSlv(g_num_data_bits);
tb_load_i <= data.randSlv(1)(1);
tb_cs_sel_i <= data.randSlv(g_num_cs_select);
tb_sclk_divsel_i <= data.randSlv(3);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
wait;
end process stim;
--------------------------------------------------------------------------------
......@@ -139,9 +139,9 @@ begin
divider_sel : process (s_divider, tb_sclk_divsel_i)
begin -- process
case tb_sclk_divsel_i is
when "000" => s_div_muxed <= s_divider(1);
when "001" => s_div_muxed <= s_divider(2);
when "010" => s_div_muxed <= s_divider(3);
when "000" => s_div_muxed <= s_divider(1);
when "001" => s_div_muxed <= s_divider(2);
when "010" => s_div_muxed <= s_divider(3);
when "011" => s_div_muxed <= s_divider(4);
when "100" => s_div_muxed <= s_divider(5);
when "101" => s_div_muxed <= s_divider(6);
......@@ -197,10 +197,10 @@ begin
end if;
end if;
end process;
data_out : process(tb_clk_i)
begin
if rising_edge(tb_clk_i) then
if rising_edge(tb_clk_i) then
if tb_rst_n_i = '0' then
s_data_o <= (others=>'0');
else
......
testbench/common/gc_simple_spi_master/README.md
View file @ 044a3bb2
......@@ -2,7 +2,7 @@ This is a testbench to verify the gc_dual_pi_controler core. It uses GHDL simula
- g_div_ratio_log2 : Clock division ratio
- g_num_data_bits : Number of data bits per transfer
Regarding the assigned values in these generic, there can be various combinations (testcases), some of them are presented here (1,1), (2,2), (2,4), (3,4).
Regarding the assigned values in these generic, there can be various combinations (testcases), some of them are presented here (1,1), (2,2), (2,4), (3,4).
The testbench, receives random input data (with random seeds). A clock divider counter generates s_tick which is used to control the FSM. One assertion exist in the testbench to bring self-checking capabilities in it and checks, if the incoming data is equal with the outcoming data, in the end of the FSM process.
FSM coverage is covered through the use of OSVVM methodology, where the transition of the states is being checked in every clock and the reports are shown in the end.
FSM coverage is covered through the use of OSVVM methodology, where the transition of the states is being checked in every clock and the reports are shown in the end.
testbench/common/gc_simple_spi_master/tb_gc_simple_spi_master.vhd
View file @ 044a3bb2
......@@ -6,29 +6,29 @@
-- Author : Konstantinos Blantos
-- Company : CERN (BE-CEM-EDL)
-- Created : 2021-12-13
-- Last update:
-- Last update:
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Testbench for a simple SPI master (bus-less).
-- Description: Testbench for a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -44,7 +44,7 @@ use osvvm.CoveragePkg.all;
entity tb_gc_simple_spi_master is
generic (
g_seed : natural;
g_seed : natural := 1992;
g_div_ratio_log2 : integer := 2;
g_num_data_bits : integer := 2);
end entity;
......@@ -75,10 +75,10 @@ architecture tb of tb_gc_simple_spi_master is
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal s_state : t_state;
signal s_cnt : unsigned(4 downto 0) := (others=>'0');
-- Shared variable used for FSM coverage
-- Shared variable used for FSM coverage
shared variable sv_cover : covPType;
--------------------------------------------------------------------------------
-- Procedures used for fsm coverage --
--------------------------------------------------------------------------------
......@@ -94,8 +94,8 @@ architecture tb of tb_gc_simple_spi_master is
GenBin(t_state'pos(prev)),
GenBin(t_state'pos(curr)));
end procedure;
-- illegal
-- illegal
procedure fsm_covadd_illegal (
name : in string;
covdb : inout covPType ) is
......@@ -137,27 +137,27 @@ begin
data_o => tb_data_o,
spi_cs_n_o => tb_spi_cs_n_o,
spi_sclk_o => tb_spi_sclk_o,
spi_mosi_o => s_mosi,
spi_miso_i => s_mosi);
spi_mosi_o => s_mosi,
spi_miso_i => s_mosi);
-- Clock generation
clk_sys_proc : process
begin
clk_sys_proc : process
begin
while not stop loop
tb_clk_sys_i <= '1';
wait for C_CLK_SYS_PERIOD/2;
tb_clk_sys_i <= '0';
wait for C_CLK_SYS_PERIOD/2;
end loop;
wait;
end process clk_sys_proc;
tb_clk_sys_i <= '1';
wait for C_CLK_SYS_PERIOD/2;
tb_clk_sys_i <= '0';
wait for C_CLK_SYS_PERIOD/2;
end loop;
wait;
end process clk_sys_proc;
-- Reset generation
tb_rst_n_i <= '0', '1' after 4*C_CLK_SYS_PERIOD;
-- Slave clocks in the data on risigin SCLK edge
tb_cpol_i <= '1';
-- Stimulus
stim : process
variable ncycles : natural;
......@@ -165,18 +165,18 @@ begin
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while NOW < 4 ms loop
while NOW < 1 ms loop
wait until (rising_edge(tb_clk_sys_i) and tb_rst_n_i = '1');
tb_start_i <= data.randSlv(1)(1);
tb_cs_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
wait;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
wait;
end process stim;
-- Stimulus for data
-- Stimulus for data
stim_data : process
variable data : RandomPType;
variable ncycles : natural;
......@@ -219,34 +219,34 @@ begin
s_cnt <= (others=>'0');
else
case s_state is
when IDLE =>
when IDLE =>
s_cnt <= (others=>'0');
if tb_start_i = '1' then
if tb_start_i = '1' then
s_state <= TX_CS;
end if;
when TX_CS =>
if s_tick='1' then
s_state <=TX_DAT1;
when TX_CS =>
if s_tick='1' then
s_state <=TX_DAT1;
end if;
when TX_DAT1 =>
if s_tick='1' then
s_state <= TX_SCK1;
when TX_DAT1 =>
if s_tick='1' then
s_state <= TX_SCK1;
end if;
when TX_SCK1 =>
if s_tick='1' then
when TX_SCK1 =>
if s_tick='1' then
s_state <= TX_DAT2;
s_cnt <= s_cnt + 1;
end if;
when TX_DAT2 =>
if s_tick='1' then
s_state <= TX_SCK2;
when TX_DAT2 =>
if s_tick='1' then
s_state <= TX_SCK2;
end if;
when TX_SCK2 =>
when TX_SCK2 =>
if s_tick='1' then
if s_cnt=g_num_data_bits then
s_state <= TX_CS2;
......@@ -254,28 +254,28 @@ begin
s_state <= TX_DAT1;
end if;
end if;
when TX_CS2 =>
if s_tick='1' then
s_state <= TX_GAP;
when TX_CS2 =>
if s_tick='1' then
s_state <= TX_GAP;
end if;
when TX_GAP =>
if s_tick='1' then
s_state <= IDLE;
when TX_GAP =>
if s_tick='1' then
s_state <= IDLE;
end if;
when others =>
null;
null;
end case;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
process
begin
while not stop loop
......@@ -315,11 +315,11 @@ begin
end process;
fsm_covcollect(tb_rst_n_i, tb_clk_sys_i, s_state,sv_cover);
-- coverage report
cov_report : process
begin
wait until stop ;
wait until stop ;
sv_cover.writebin;
end process;
......
testbench/common/gc_sync/tb_gc_sync.vhd
View file @ 044a3bb2
......@@ -37,36 +37,36 @@ use osvvm.CoveragePkg.all;
entity tb_gc_sync is
generic (
g_seed : natural;
g_SYNC_EDGE : string := "positive");
g_SYNC_EDGE : string := "positive");
end entity;
architecture tb of tb_gc_sync is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_i : std_logic;
signal tb_d_i : std_logic := '0';
signal tb_q_o : std_logic;
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_i : std_logic;
signal tb_d_i : std_logic := '0';
signal tb_q_o : std_logic;
signal stop : boolean;
-- Shared variables, used for coverage
shared variable cp_rst_i : covPType;
shared variable cp_rst_i : covPType;
begin
--Unit Under Test
UUT : entity work.gc_sync
generic map (
g_SYNC_EDGE => g_SYNC_EDGE)
port map (
clk_i => tb_clk_i,
rst_n_a_i => tb_rst_i,
d_i => tb_d_i,
q_o => tb_q_o);
UUT : entity work.gc_sync
generic map (
g_SYNC_EDGE => g_SYNC_EDGE)
port map (
clk_i => tb_clk_i,
rst_n_a_i => tb_rst_i,
d_i => tb_d_i,
q_o => tb_q_o);
--Clock generation
clk_i_process : process
......@@ -79,8 +79,8 @@ begin
end loop;
wait;
end process;
-- Reset generation
-- Reset generation
tb_rst_i <= '0', '1' after 2*C_CLK_PERIOD;
-- Randomized stimulus
......@@ -117,7 +117,7 @@ begin
else
wait for 2*C_CLK_PERIOD;
assert (tb_q_o = '0')
report "output not de-asserted after two clocks" severity failure;
report "output not de-asserted after two clocks" severity failure;
end if;
end if;
wait;
......@@ -128,8 +128,8 @@ begin
-------------------------------------------------------------------------------
--sets up coverpoint bins
InitCoverage: process
begin
InitCoverage: process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
wait;
end process InitCoverage;
......
testbench/common/gc_sync_ffs/tb_gc_sync_ffs.vhd
View file @ 044a3bb2
......@@ -7,7 +7,7 @@
-- unit name: gc_sync_ffs
--
-- description: Testbench that verifies the Synchronizer chain and edge detector.
-- All the registers in the chain are cleared at reset.
-- All the registers in the chain are cleared at reset.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2020
......@@ -43,7 +43,7 @@ use osvvm.CoveragePkg.all;
entity tb_gc_sync_ffs is
generic (
g_seed : natural;
g_SYNC_EDGE : string := "positive");
g_SYNC_EDGE : string := "positive");
end entity;
--==============================================================================
......@@ -53,31 +53,31 @@ end entity;
architecture tb of tb_gc_sync_ffs is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
constant C_CLK_PERIOD : time := 10 ns;
--Signals
signal tb_clk_i : std_logic := '1'; -- clock from the destination clock domain
--Signals
signal tb_clk_i : std_logic := '1'; -- clock from the destination clock domain
signal tb_rst_n_i : std_logic; -- async reset
signal tb_data_i : std_logic := '0'; -- async input
signal tb_synced_o : std_logic; -- synchronized output
signal tb_npulse_o : std_logic; -- negative edge detect output
signal tb_ppulse_o : std_logic; -- positive edge detect output
signal stop : boolean;
signal stop : boolean;
-- Shared variable used for coverage
shared variable cp_rst_i : covPType;
shared variable cp_rst_i : covPType;
begin
--Unit Under Test
UUT : entity work.gc_sync_ffs
generic map (
--Unit Under Test
UUT : entity work.gc_sync_ffs
generic map (
g_SYNC_EDGE => g_SYNC_EDGE)
port map (
clk_i => tb_clk_i,
port map (
clk_i => tb_clk_i,
rst_n_i => tb_rst_n_i,
data_i => tb_data_i,
synced_o => tb_synced_o,
data_i => tb_data_i,
synced_o => tb_synced_o,
npulse_o => tb_npulse_o,
ppulse_o => tb_ppulse_o);
......@@ -93,19 +93,19 @@ begin
wait;
end process;
tb_rst_n_i <= '0', '1' after 2 * C_CLK_PERIOD;
tb_rst_n_i <= '0', '1' after 2 * C_CLK_PERIOD;
-- Randomized stimulus
Stim: process
variable data : RandomPType;
variable ncycles : natural;
variable data : RandomPType;
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING Slave] with seed = " & to_string(g_seed);
while (NOW < 1 ms) loop
wait until (rising_edge(tb_clk_i));
tb_data_i <= data.randSlv(1)(1);
nCycles := nCycles + 1;
wait until (rising_edge(tb_clk_i));
tb_data_i <= data.randSlv(1)(1);
nCycles := nCycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(nCycles);
STOP <= TRUE;
......@@ -117,42 +117,42 @@ begin
-- Assertions - Self Checking --
--------------------------------------------------------------------------------
-- Assertion to check if the output
-- pulse is synchronized
sync_output : process
begin
if (g_SYNC_EDGE = "positive") then
if (tb_data_i = '1') then
wait for 3*C_CLK_PERIOD;
assert (tb_synced_o = '1'
and tb_ppulse_o = '1' and tb_npulse_o='0')
report "the output is not synchronized"
severity failure;
end if;
elsif (g_SYNC_EDGE = "negative") then
if (tb_data_i = '1') then
wait for 3 *C_CLK_PERIOD;
assert (tb_synced_o = '1'
and tb_ppulse_o = '1' and tb_npulse_o='0')
report "the output is not synchronized"
severity failure;
end if;
else
assert (g_SYNC_EDGE="positive" or g_SYNC_EDGE="negative")
report "Wrong value for g_SYNC_EDGE"
severity failure;
end if;
wait;
end process sync_output;
-- Assertion to check if the output
-- pulse is synchronized
sync_output : process
begin
if (g_SYNC_EDGE = "positive") then
if (tb_data_i = '1') then
wait for 3*C_CLK_PERIOD;
assert (tb_synced_o = '1'
and tb_ppulse_o = '1' and tb_npulse_o='0')
report "the output is not synchronized"
severity failure;
end if;
elsif (g_SYNC_EDGE = "negative") then
if (tb_data_i = '1') then
wait for 3 *C_CLK_PERIOD;
assert (tb_synced_o = '1'
and tb_ppulse_o = '1' and tb_npulse_o='0')
report "the output is not synchronized"
severity failure;
end if;
else
assert (g_SYNC_EDGE="positive" or g_SYNC_EDGE="negative")
report "Wrong value for g_SYNC_EDGE"
severity failure;
end if;
wait;
end process sync_output;
--------------------------------------------------------------------------------
-- Coverage --
--------------------------------------------------------------------------------
--sets up coverpoint bins
InitCoverage: process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
--sets up coverpoint bins
InitCoverage: process
begin
cp_rst_i.AddBins("reset has asserted", ONE_BIN);
wait;
end process InitCoverage;
......
testbench/common/gc_sync_register/tb_gc_sync_register.vhd
View file @ 044a3bb2
......@@ -42,9 +42,9 @@ use osvvm.CoveragePkg.all;
--=============================================================================
entity tb_gc_sync_register is
generic (
generic (
g_seed : natural;
g_WIDTH : integer := 8);
g_WIDTH : integer := 8);
end entity;
--==============================================================================
......@@ -54,59 +54,59 @@ end entity;
architecture tb of tb_gc_sync_register is
-- Constants
constant C_CLK_PERIOD : time := 10 ns;
constant C_CLK_PERIOD : time := 10 ns;
-- Signals
signal tb_clk_i : std_logic;
signal tb_rst_n_a_i : std_logic;
signal tb_d_i : std_logic_vector(g_WIDTH-1 downto 0) := (others=>'0');
signal tb_q_o : std_logic_vector(g_WIDTH-1 downto 0);
signal tb_clk_i : std_logic;
signal tb_rst_n_a_i : std_logic;
signal tb_d_i : std_logic_vector(g_WIDTH-1 downto 0) := (others=>'0');
signal tb_q_o : std_logic_vector(g_WIDTH-1 downto 0);
signal s_data_o : std_logic_vector(g_WIDTH-1 downto 0) := (others=>'0');
signal s_data_0 : std_logic_vector(g_WIDTH-1 downto 0) := (others=>'0');
signal stop : boolean;
signal stop : boolean;
begin
-- Unit Under Test
UUT : entity work.gc_sync_register
generic map (
g_WIDTH => g_WIDTH)
port map (
clk_i => tb_clk_i,
rst_n_a_i => tb_rst_n_a_i,
d_i => tb_d_i,
q_o => tb_q_o);
clk_i : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process;
tb_rst_n_a_i <= '0', '1' after 2 * C_CLK_PERIOD;
-- Unit Under Test
UUT : entity work.gc_sync_register
generic map (
g_WIDTH => g_WIDTH)
port map (
clk_i => tb_clk_i,
rst_n_a_i => tb_rst_n_a_i,
d_i => tb_d_i,
q_o => tb_q_o);
clk_i : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process;
tb_rst_n_a_i <= '0', '1' after 2 * C_CLK_PERIOD;
--Stimulus
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
stim : process
variable ncycles : natural;
variable data : RandomPType;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
while (NOW < 1 ms) loop
wait until (rising_edge(tb_clk_i));
tb_d_i <= data.randSlv(g_WIDTH);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
while (NOW < 1 ms) loop
wait until (rising_edge(tb_clk_i));
tb_d_i <= data.randSlv(g_WIDTH);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
report "Test PASS!";
stop <= TRUE;
wait;
end process stim;
stop <= TRUE;
wait;
end process stim;
--------------------------------------------------------------------------------
-- Assertions - Self Checking --
......
testbench/common/gc_sync_word_rd/tb_gc_sync_word_rd.vhd
View file @ 044a3bb2
......@@ -52,7 +52,7 @@ use osvvm.CoveragePkg.all;
entity tb_gc_sync_word_rd is
generic (
g_seed : natural;
g_WIDTH : positive := 8);
g_WIDTH : positive := 8);
end entity;
--==============================================================================
......@@ -82,32 +82,32 @@ architecture tb of tb_gc_sync_word_rd is
shared variable cp_rst_out_i : covPType;
begin
--Unit Under Test
UUT : entity work.gc_sync_word_rd
generic map (
g_WIDTH => g_WIDTH)
port map (
clk_out_i => tb_clk_out_i,
rst_out_n_i => tb_rst_out_n_i,
clk_in_i => tb_clk_in_i,
rst_in_n_i => tb_rst_in_n_i,
data_in_i => tb_data_in_i,
rd_out_i => tb_rd_out_i,
ack_out_o => tb_ack_out_o,
data_out_o => tb_data_out_o,
rd_in_o => tb_rd_in_o);
clk_out_i => tb_clk_out_i,
rst_out_n_i => tb_rst_out_n_i,
clk_in_i => tb_clk_in_i,
rst_in_n_i => tb_rst_in_n_i,
data_in_i => tb_data_in_i,
rd_out_i => tb_rd_out_i,
ack_out_o => tb_ack_out_o,
data_out_o => tb_data_out_o,
rd_in_o => tb_rd_in_o);
-- Input clock/reset generation
clk_in : process
begin
while not stop loop
tb_clk_in_i <= '0';
wait for C_CLK_IN_PERIOD/2;
tb_clk_in_i <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
while not stop loop
tb_clk_in_i <= '0';
wait for C_CLK_IN_PERIOD/2;
tb_clk_in_i <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
end process clk_in;
tb_rst_in_n_i <= '0', '1' after 2 * C_CLK_IN_PERIOD;
......@@ -115,47 +115,47 @@ begin
-- Output clock/reset
clk_out : process
begin
while stop = FALSE loop
tb_clk_out_i <= '0';
wait for C_CLK_OUT_PERIOD/2;
tb_clk_out_i <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
while stop = FALSE loop
tb_clk_out_i <= '0';
wait for C_CLK_OUT_PERIOD/2;
tb_clk_out_i <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
end process clk_out;
tb_rst_out_n_i <= '0', '1' after 2 * C_CLK_OUT_PERIOD;
-- Randomized stimulus
stim : process
variable data : RandomPType;
variable ncycles : natural;
variable data : RandomPType;
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING Slave] with seed = " & to_string(g_seed);
while (NOW < 1 ms) loop
wait until (rising_edge(tb_clk_in_i) and tb_rst_in_n_i='1');
wait until (rising_edge(tb_clk_in_i) and tb_rst_in_n_i='1');
if (tb_rd_in_o='1') then
tb_rd_out_i <= '1';
tb_rd_out_i <= '1';
else
tb_rd_out_i <= '0';
end if;
if (tb_rd_out_i = '1' and tb_clk_in_i = '1') then
tb_data_in_i <= data.randSlv(g_WIDTH);
if (tb_rd_out_i = '1' and tb_clk_in_i = '1') then
tb_data_in_i <= data.randSlv(g_WIDTH);
end if;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
report "Test PASS!";
stop <= TRUE;
wait;
stop <= TRUE;
wait;
end process stim;
--------------------------------------------------------------------------------
-- Assertions - Self Checking --
--------------------------------------------------------------------------------
--Assertions
--Assertions
self_check : process
begin
while not stop loop
......@@ -171,10 +171,10 @@ begin
--------------------------------------------------------------------------------
--sets up coverpoint bins
InitCoverage: process
begin
InitCoverage: process
begin
cp_rst_in_i.AddBins("input reset has been asserted", ONE_BIN);
cp_rst_out_i.AddBins("output reset has been asserted", ONE_BIN);
cp_rst_out_i.AddBins("output reset has been asserted", ONE_BIN);
wait;
end process InitCoverage;
......@@ -190,15 +190,15 @@ begin
begin
loop
wait on tb_rst_out_n_i;
cp_rst_out_i.ICover (to_integer(tb_rst_out_n_i = '1'));
cp_rst_out_i.ICover (to_integer(tb_rst_out_n_i = '1'));
end loop;
end process;
CoverReport: process
begin
wait until STOP;
cp_rst_in_i.writebin;
cp_rst_out_i.writebin;
cp_rst_in_i.writebin;
cp_rst_out_i.writebin;
end process;
end tb;
testbench/common/gc_sync_word_wr/tb_gc_sync_word_wr.vhd
View file @ 044a3bb2
......@@ -103,11 +103,11 @@ begin
begin
while not stop loop
tb_clki <= '0';
wait for C_CLK_IN_PERIOD/2;
tb_clki <= '1';
wait for C_CLK_OUT_PERIOD/2;
wait for C_CLK_IN_PERIOD/2;
tb_clki <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
wait;
end process clk_in;
tb_rsti <= '0', '1' after 3 * C_CLK_IN_PERIOD;
......@@ -116,52 +116,52 @@ begin
clk_out : process
begin
while not stop loop
tb_clko <= '0';
wait for C_CLK_OUT_PERIOD/2;
tb_clko <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
tb_clko <= '0';
wait for C_CLK_OUT_PERIOD/2;
tb_clko <= '1';
wait for C_CLK_OUT_PERIOD/2;
end loop;
wait;
end process clk_out;
tb_rsto <= '0', '1' after 4 * C_CLK_OUT_PERIOD;
-- Randomized stimulus
stim : process
variable data : RandomPType;
variable ncycles : natural;
variable data : RandomPType;
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING Slave] with seed = " & to_string(g_seed);
tb_wri <= '0';
wait until tb_rsti = '1';
while (NOW < 1 ms) loop
wait until (rising_edge(tb_clki) and tb_busy='0');
tb_din <= data.randSlv(g_WIDTH);
wait until (rising_edge(tb_clki) and tb_busy='0');
tb_din <= data.randSlv(g_WIDTH);
tb_wri <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
report "Test PASS!";
stop <= TRUE;
wait;
stop <= TRUE;
wait;
end process stim;
--------------------------------------------------------------------------------
-- Assertions - Self Checking --
--------------------------------------------------------------------------------
-- Assertion to verify the behavior of ACK signal
-- Assertion to verify the behavior of ACK signal
data_o_check : process
begin
begin
if rising_edge(tb_clki) then
assert (tb_ack /= tb_wro)
report "ACK and write enable equal" severity failure;
assert (tb_ack /= tb_busy)
report "ACK while still busy" severity failure;
end if;
wait;
end process data_o_check;
wait;
end process data_o_check;
--Self-Checking: Checks that the output data is the
--same as the input data
......@@ -180,7 +180,7 @@ begin
wr_side : process (tb_clki)
begin
if rising_edge(tb_clki) then
if (tb_busy= '0') then
if (tb_busy= '0') then
s_data_o <= tb_din;
end if;
end if;
......@@ -202,10 +202,10 @@ begin
--------------------------------------------------------------------------------
--sets up coverpoint bins
InitCoverage: process
begin
InitCoverage: process
begin
cp_rst_in_i.AddBins("input reset has been asserted", ONE_BIN);
cp_rst_out_i.AddBins("output reset has been asserted", ONE_BIN);
cp_rst_out_i.AddBins("output reset has been asserted", ONE_BIN);
wait;
end process InitCoverage;
......@@ -214,10 +214,10 @@ begin
begin
loop
wait on tb_rsti;
wait on tb_rsto;
wait for C_CLK_IN_PERIOD;
wait on tb_rsto;
wait for C_CLK_IN_PERIOD;
cp_rst_in_i.ICover (to_integer(tb_rsti = '1'));
cp_rst_out_i.ICover (to_integer(tb_rsto = '1'));
cp_rst_out_i.ICover (to_integer(tb_rsto = '1'));
end loop;
end process Sample;
......@@ -226,7 +226,7 @@ begin
begin
wait until STOP;
cp_rst_in_i.writebin;
cp_rst_out_i.writebin;
cp_rst_out_i.writebin;
end process;
end tb;
......
testbench/common/gc_word_packer/tb_gc_word_packer.vhd
View file @ 044a3bb2
......@@ -6,32 +6,32 @@
-- Author : Konstantinos Blantos
-- Company : CERN (BE-CEM-EDL)
-- Created : 2021-12-21
-- Last update:
-- Last update:
-- Platform : FPGA-generic
-- Standard : VHDL 2008
-------------------------------------------------------------------------------
-- Description: Testbench for gc_word_packer. Packs/unpacks g_input_width-sized
-- word(s) into g_output_width-sized word(s). Data is packed starting from the
-- least significant word. Packet width must be integer multiple of the
-- word(s) into g_output_width-sized word(s). Data is packed starting from the
-- least significant word. Packet width must be integer multiple of the
-- unpacked width.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2022 CERN / BE-CEM-EDL
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -55,7 +55,7 @@ entity tb_gc_word_packer is
end entity;
architecture tb of tb_gc_word_packer is
-- functions
function f_max(a : integer; b : integer) return integer is
begin
......@@ -118,38 +118,38 @@ begin
q_req_i => tb_q_req_i);
-- clock and reset behavior
clk_proc : process
begin
while STOP = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
clk_proc : process
begin
while STOP = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
tb_rst_n_i <= '0', '1' after 2*C_CLK_PERIOD;
-- stimulus
stim : process
variable data : RandomPType;
variable data : RandomPType;
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & to_string(g_seed);
wait until tb_rst_n_i = '1';
while (NOW < 4 ms) loop
wait until (rising_edge(tb_clk_i));
wait until (rising_edge(tb_clk_i));
tb_d_i <= data.randSlv(g_input_width);
tb_d_valid_i <= '1' when tb_d_req_o='1' else '0';
tb_q_req_i <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
wait;
end process stim;
-- Delayed q_req_i for one clock cycle
......@@ -163,13 +163,13 @@ begin
end if;
end if;
end process p_del_q_req_i;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
-- Below it is checked that the generics are valid compared to the specification
-- and that the core is working properly. Doing the packing and unpacking as it
-- and that the core is working properly. Doing the packing and unpacking as it
-- is expected. This is tested in three different cases regarding the data width
-- When Input is bigger than the output
......@@ -217,7 +217,7 @@ begin
s_empty <= '1';
else
if(s_cnt = c_sreg_entries-1 and tb_d_valid_i = '0' and tb_q_req_d0 = '1') then
s_empty <= '1';
s_empty <= '1';
elsif(tb_d_valid_i = '1') then
s_empty <= '0';
end if;
......@@ -226,7 +226,7 @@ begin
end process;
-- output data generation
s_dat <= s_data_i(s_cnt*g_output_width+g_output_width-1 downto s_cnt*g_output_width) when (s_empty= '0' and tb_q_req_d0 = '1')
s_dat <= s_data_i(s_cnt*g_output_width+g_output_width-1 downto s_cnt*g_output_width) when (s_empty= '0' and tb_q_req_d0 = '1')
else tb_d_i(g_output_width-1 downto 0) when (tb_q_req_d0 = '1' and tb_d_valid_i = '1')
else (others=>'X');
......@@ -251,7 +251,7 @@ begin
assert(g_input_width mod g_output_width = g_input_width)
report "Input smaller than output: not a multiple integer of output width"
severity failure;
-- counter calculation to find how many packets, the output will have
cnt_data : process(tb_clk_i)
begin
......@@ -307,7 +307,7 @@ begin
if (rising_edge(tb_clk_i)) then
assert (tb_d_i = tb_q_o)
report "DATA mismatch" severity failure;
assert (tb_d_valid_i = tb_q_valid_o)
report "Data Valid mismatch" severity failure;
......
testbench/genrams/common/inferred_async_fifo/tb_inferred_async_fifo.vhd
View file @ 044a3bb2
......@@ -6,7 +6,7 @@
--
-- unit name: tb_inferred_async_fifo
--
-- description: Testbench for the parametrizable asynchronous FIFO
-- description: Testbench for the parametrizable asynchronous FIFO
-- Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
......@@ -35,7 +35,7 @@ use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
--OSVMM library
--OSVMM library
library osvvm;
use osvvm.RandomPkg.all;
use osvvm.CoveragePkg.all;
......@@ -93,7 +93,7 @@ architecture tb of tb_inferred_async_fifo is
signal stop : boolean;
signal tb_wr : std_logic := '0';
signal tb_rd : std_logic := '0';
-- 2D array is for self-checking purpose
type t_array is array (0 to g_size)
of std_logic_vector(g_data_width-1 downto 0);
......@@ -141,7 +141,7 @@ begin
wr_almost_full_o => tb_wr_almost_full_o,
wr_count_o => tb_wr_count_o,
clk_rd_i => tb_clk_rd_i,
q_o => tb_q_o,
q_o => tb_q_o,
rd_i => tb_rd_i,
rd_empty_o => tb_rd_empty_o,
rd_full_o => tb_rd_full_o,
......@@ -149,65 +149,65 @@ begin
rd_almost_full_o => tb_rd_almost_full_o,
rd_count_o => tb_rd_count_o);
--WR clock
wr_clk : process
begin
while stop = FALSE loop
tb_clk_wr_i <= '1';
wait for C_CLK_WR_PERIOD/2;
tb_clk_wr_i <= '0';
wait for C_CLK_WR_PERIOD/2;
end loop;
wait;
end process wr_clk;
--WR clock
wr_clk : process
begin
while stop = FALSE loop
tb_clk_wr_i <= '1';
wait for C_CLK_WR_PERIOD/2;
tb_clk_wr_i <= '0';
wait for C_CLK_WR_PERIOD/2;
end loop;
wait;
end process wr_clk;
-- RD clock
rd_clk : process
begin
while stop = FALSE loop
tb_clk_rd_i <= '1';
wait for C_CLK_RD_PERIOD/2;
tb_clk_rd_i <= '0';
wait for C_CLK_RD_PERIOD/2;
end loop;
wait;
end process rd_clk;
rd_clk : process
begin
while stop = FALSE loop
tb_clk_rd_i <= '1';
wait for C_CLK_RD_PERIOD/2;
tb_clk_rd_i <= '0';
wait for C_CLK_RD_PERIOD/2;
end loop;
wait;
end process rd_clk;
tb_rst_n_i <= '0', '1' after 4*C_CLK_WR_PERIOD;
-- Stimulus for write side input data
stim_wr : process
stim_wr : process
variable data : RandomPType;
variable ncycles : natural;
begin
variable ncycles : natural;
begin
data.InitSeed(g_seed_wr);
report "[STARTING - WR] with seed = " & integer'image(g_seed_wr);
while (NOW < 2 ms ) loop
wait until (rising_edge (tb_clk_wr_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
while (NOW < 2 ms ) loop
wait until (rising_edge (tb_clk_wr_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
tb_wr <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "[WR] Number of simulation cycles = " & to_string(ncycles);
ncycles := ncycles + 1;
end loop;
report "[WR] Number of simulation cycles = " & to_string(ncycles);
report "Test PASS!";
stop <= true;
stop <= true;
wait;
end process stim_wr;
-- Stimulus for read side input data
stim_rd : process
stim_rd : process
variable data : RandomPType;
variable ncycles : natural;
begin
variable ncycles : natural;
begin
data.InitSeed(g_seed_rd);
report "[STARTING - RD] with seed = " & integer'image(g_seed_rd);
while (stop = FALSE) loop
wait until (rising_edge (tb_clk_rd_i) and tb_rst_n_i = '1');
while (stop = FALSE) loop
wait until (rising_edge (tb_clk_rd_i) and tb_rst_n_i = '1');
tb_rd <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "[RD] Number of simulation cycles = " & to_string(ncycles);
wait;
ncycles := ncycles + 1;
end loop;
report "[RD] Number of simulation cycles = " & to_string(ncycles);
wait;
end process stim_rd;
-- Write and Read enable
......@@ -254,7 +254,7 @@ begin
begin
if rising_edge(tb_clk_wr_i) then
assert (NOT(tb_we_i = '1' AND tb_wr_full_o = '1'))
report "WR SIDE: Can not write in a full FIFO"
report "WR SIDE: Can not write in a full FIFO"
severity failure;
end if;
end process;
......@@ -286,7 +286,7 @@ begin
end if;
end process;
no_almost_empty_full : if (g_with_wr_almost_empty = false
no_almost_empty_full : if (g_with_wr_almost_empty = false
or g_with_rd_almost_empty = false
or g_with_wr_almost_full= false
or g_with_rd_almost_full= false) generate
......@@ -312,7 +312,7 @@ begin
end generate;
almost_empty_full : if (g_with_wr_almost_empty = true
almost_empty_full : if (g_with_wr_almost_empty = true
or g_with_rd_almost_empty = true
or g_with_wr_almost_full= true
or g_with_rd_almost_full= true)
......@@ -321,7 +321,7 @@ begin
self_check_rd : process
begin
while (stop = FALSE) loop
wait until rising_edge(tb_clk_rd_i);
wait until rising_edge(tb_clk_rd_i);
if (tb_rd_i = '1' ) then
wait for C_CLK_RD_PERIOD;
if (s_arr(s_rd_ptr) = tb_q_o) then
......
testbench/genrams/common/inferred_sync_fifo/tb_inferred_sync_fifo.vhd
View file @ 044a3bb2
......@@ -47,7 +47,7 @@ entity tb_inferred_sync_fifo is
g_seed : natural;
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_show_ahead : boolean;
g_show_ahead_legacy_mode : boolean;
g_with_empty : boolean := true;
g_with_full : boolean := true;
......@@ -124,9 +124,9 @@ begin
clk_i => tb_clk_i,
d_i => tb_d_i,
we_i => tb_we_i,
q_o => tb_q_o,
q_o => tb_q_o,
rd_i => tb_rd_i,
empty_o => tb_empty_o,
empty_o => tb_empty_o,
full_o => tb_full_o,
almost_empty_o => tb_almost_empty_o,
almost_full_o => tb_almost_full_o,
......@@ -134,37 +134,37 @@ begin
);
--clock and reset
clk_proc : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
clk_proc : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
wait;
end process clk_proc;
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
-- Stimulus for input data
stim : process
stim : process
variable data : RandomPType;
variable ncycles : natural;
begin
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & integer'image(g_seed);
while (NOW < 4 ms ) loop
wait until (rising_edge (tb_clk_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
while (NOW < 4 ms ) loop
wait until (rising_edge (tb_clk_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
tb_wr <= data.randSlv(1)(1);
tb_rd <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
wait;
end process stim;
-- Write and Read enable
......@@ -211,7 +211,7 @@ begin
begin
if rising_edge(tb_clk_i) then
assert (NOT(tb_we_i = '1' AND tb_full_o = '1'))
report "Can not write in a full FIFO"
report "Can not write in a full FIFO"
severity failure;
end if;
end process;
......
testbench/genrams/generic/generic_async_fifo/tb_generic_async_fifo.vhd
View file @ 044a3bb2
......@@ -38,7 +38,7 @@ use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
--OSVMM library
--OSVMM library
library osvvm;
use osvvm.RandomPkg.all;
use osvvm.CoveragePkg.all;
......@@ -104,7 +104,7 @@ architecture tb of tb_generic_async_fifo is
signal stop : boolean;
signal tb_wr : std_logic := '0';
signal tb_rd : std_logic := '0';
-- 2D array is for self-checking purpose
type t_array is array (0 to g_size)
of std_logic_vector(g_data_width-1 downto 0);
......@@ -152,7 +152,7 @@ begin
wr_almost_full_o => tb_wr_almost_full_o,
wr_count_o => tb_wr_count_o,
clk_rd_i => tb_clk_rd_i,
q_o => tb_q_o,
q_o => tb_q_o,
rd_i => tb_rd_i,
rd_empty_o => tb_rd_empty_o,
rd_full_o => tb_rd_full_o,
......@@ -160,65 +160,65 @@ begin
rd_almost_full_o => tb_rd_almost_full_o,
rd_count_o => tb_rd_count_o);
--WR clock
wr_clk : process
begin
while stop = FALSE loop
tb_clk_wr_i <= '1';
wait for C_CLK_WR_PERIOD/2;
tb_clk_wr_i <= '0';
wait for C_CLK_WR_PERIOD/2;
end loop;
wait;
end process wr_clk;
--WR clock
wr_clk : process
begin
while stop = FALSE loop
tb_clk_wr_i <= '1';
wait for C_CLK_WR_PERIOD/2;
tb_clk_wr_i <= '0';
wait for C_CLK_WR_PERIOD/2;
end loop;
wait;
end process wr_clk;
-- RD clock
rd_clk : process
begin
while stop = FALSE loop
tb_clk_rd_i <= '1';
wait for C_CLK_RD_PERIOD/2;
tb_clk_rd_i <= '0';
wait for C_CLK_RD_PERIOD/2;
end loop;
wait;
end process rd_clk;
rd_clk : process
begin
while stop = FALSE loop
tb_clk_rd_i <= '1';
wait for C_CLK_RD_PERIOD/2;
tb_clk_rd_i <= '0';
wait for C_CLK_RD_PERIOD/2;
end loop;
wait;
end process rd_clk;
tb_rst_n_i <= '0', '1' after 4*C_CLK_WR_PERIOD;
-- Stimulus for write side input data
stim_wr : process
stim_wr : process
variable data : RandomPType;
variable ncycles : natural;
begin
variable ncycles : natural;
begin
data.InitSeed(g_seed_wr);
report "[STARTING - WR] with seed = " & integer'image(g_seed_wr);
while (NOW < 1 ms ) loop
wait until (rising_edge (tb_clk_wr_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
while (NOW < 1 ms ) loop
wait until (rising_edge (tb_clk_wr_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
tb_wr <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
wait;
end process stim_wr;
-- Stimulus for read side input data
stim_rd : process
stim_rd : process
variable data : RandomPType;
variable ncycles : natural;
begin
variable ncycles : natural;
begin
data.InitSeed(g_seed_rd);
report "[STARTING - RD] with seed = " & integer'image(g_seed_rd);
while (stop = FALSE) loop
wait until (rising_edge (tb_clk_rd_i) and tb_rst_n_i = '1');
while (stop = FALSE) loop
wait until (rising_edge (tb_clk_rd_i) and tb_rst_n_i = '1');
tb_rd <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
wait;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
wait;
end process stim_rd;
-- Write and Read enable
......@@ -265,7 +265,7 @@ begin
begin
if rising_edge(tb_clk_wr_i) then
assert (NOT(tb_we_i = '1' AND tb_wr_full_o = '1'))
report "WR SIDE: Can not write in a full FIFO"
report "WR SIDE: Can not write in a full FIFO"
severity failure;
end if;
end process;
......@@ -297,7 +297,7 @@ begin
end if;
end process;
no_almost_empty_full : if (g_with_wr_almost_empty = false
no_almost_empty_full : if (g_with_wr_almost_empty = false
or g_with_rd_almost_empty = false
or g_with_wr_almost_full= false
or g_with_rd_almost_full= false) generate
......@@ -323,7 +323,7 @@ begin
end generate;
almost_empty_full : if (g_with_wr_almost_empty = true
almost_empty_full : if (g_with_wr_almost_empty = true
or g_with_rd_almost_empty = true
or g_with_wr_almost_full= true
or g_with_rd_almost_full= true)
......@@ -332,7 +332,7 @@ begin
self_check_rd : process
begin
while (stop = FALSE) loop
wait until rising_edge(tb_clk_rd_i);
wait until rising_edge(tb_clk_rd_i);
if (tb_rd_i = '1' ) then
wait for C_CLK_RD_PERIOD;
if (s_arr(s_rd_ptr) = tb_q_o) then
......
testbench/genrams/generic/generic_sync_fifo/tb_generic_sync_fifo.vhd
View file @ 044a3bb2
......@@ -51,7 +51,7 @@ entity tb_generic_sync_fifo is
g_seed : natural;
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_show_ahead : boolean;
g_show_ahead_legacy_mode : boolean;
g_with_empty : boolean := true;
g_with_full : boolean := true;
......@@ -138,37 +138,37 @@ begin
);
--clock and reset
clk_proc : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
clk_proc : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
wait;
end process clk_proc;
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
tb_rst_n_i <= '0', '1' after 4*C_CLK_PERIOD;
-- Stimulus for input data
stim : process
stim : process
variable data : RandomPType;
variable ncycles : natural;
begin
variable ncycles : natural;
begin
data.InitSeed(g_seed);
report "[STARTING] with seed = " & integer'image(g_seed);
while (NOW < 4 ms ) loop
wait until (rising_edge (tb_clk_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
while (NOW < 4 ms ) loop
wait until (rising_edge (tb_clk_i) and tb_rst_n_i = '1');
tb_d_i <= data.randSlv(g_data_width);
tb_wr <= data.randSlv(1)(1);
tb_rd <= data.randSlv(1)(1);
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
ncycles := ncycles + 1;
end loop;
report "Number of simulation cycles = " & to_string(ncycles);
stop <= TRUE;
report "Test PASS!";
wait;
wait;
end process stim;
-- Write and Read enable
......
testbench/genrams/xilinx/gc_shiftreg/tb_gc_shiftreg.vhd
View file @ 044a3bb2
......@@ -43,7 +43,7 @@ use osvvm.CoveragePkg.all;
-- Entity declaration for tb_gc_shiftreg --
--=============================================================================
entity tb_gc_shiftreg is
entity tb_gc_shiftreg is
generic (
g_seed : natural;
g_size : integer);
......@@ -83,15 +83,15 @@ begin
-- Clock process
clk_proc : process
begin
while not stop loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
begin
while not stop loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
--------------------------------------------------------------------------------
-- Stimulus --
......@@ -119,10 +119,10 @@ begin
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
-- Geneerate the output data of the testbench
g_size_big : if (g_size > 32) generate
process
begin
while not stop loop
......@@ -133,15 +133,15 @@ begin
end loop;
wait;
end process;
s_q_o <= s_dat_o(to_integer(unsigned(tb_a_i)));
end generate;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
-- Assure that size is derivative of 64
assert (g_size >32 AND (g_size mod 64) = 0)
report "Wrong size" severity failure;
......
testbench/genrams/xilinx/generic_dpram_dualclock/tb_generic_dpram_dualclock.vhd
View file @ 044a3bb2
......@@ -6,10 +6,10 @@
--
-- unit name: tb_generic_dpram_dualclock
--
-- description: Testbench for a true dual-port synchronous RAM for Xilinx FPGAs
-- description: Testbench for a true dual-port synchronous RAM for Xilinx FPGAs
-- with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to
-- - byte-addressing mode (data bus width restricted to
-- multiple of 8 bits)
--
--------------------------------------------------------------------------------
......@@ -70,10 +70,10 @@ architecture tb of tb_generic_dpram_dualclock is
constant C_CLKA_PERIOD : time := 10 ns;
constant C_CLKB_PERIOD : time := 8 ns;
constant c_num_bytes : integer := (g_data_width+7)/8;
-- types
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
-- functions
impure function f_file_to_ramtype return t_ram_type is
variable tmp : t_ram_type;
......@@ -166,27 +166,27 @@ begin
-- Clocks and reset generation
clka_proc : process
begin
while stop = FALSE loop
tb_clka_i <= '1';
wait for C_CLKA_PERIOD/2;
tb_clka_i <= '0';
wait for C_CLKA_PERIOD/2;
end loop;
wait;
end process clka_proc;
clkb_proc : process
begin
while stop = FALSE loop
tb_clkb_i <= '1';
wait for C_CLKB_PERIOD/2;
tb_clkb_i <= '0';
wait for C_CLKB_PERIOD/2;
end loop;
wait;
end process clkb_proc;
clka_proc : process
begin
while stop = FALSE loop
tb_clka_i <= '1';
wait for C_CLKA_PERIOD/2;
tb_clka_i <= '0';
wait for C_CLKA_PERIOD/2;
end loop;
wait;
end process clka_proc;
clkb_proc : process
begin
while stop = FALSE loop
tb_clkb_i <= '1';
wait for C_CLKB_PERIOD/2;
tb_clkb_i <= '0';
wait for C_CLKB_PERIOD/2;
end loop;
wait;
end process clkb_proc;
tb_rst_n_i <= '0', '1' after 30 ns;
......@@ -242,15 +242,15 @@ begin
s_web_rep <= (others => tb_web_i);
s_tb_we_a <= tb_bwea_i and s_wea_rep;
s_tb_we_b <= tb_bweb_i and s_web_rep;
--------------------------------------------------------------------------------
-- Test case 1 : Byte enable & dont care/Rd first in addr conflict resolution --
--------------------------------------------------------------------------------
g_with_byte_enable_read_first : if (g_with_byte_enable = TRUE
AND (g_addr_conflict_resolution = "dont_care"
OR g_addr_conflict_resolution = "read_first")) generate
OR g_addr_conflict_resolution = "read_first")) generate
process (tb_clka_i)
begin
if rising_edge(tb_clka_i) then
......@@ -289,11 +289,11 @@ begin
--------------------------------------------------------------------------------
-- Test case 2 : No byte enable, dont care/Rd first in addr conflict resolution --
--------------------------------------------------------------------------------
g_no_byte_enable_read_first : if (g_with_byte_enable = FALSE
AND (g_addr_conflict_resolution = "read_first"
OR g_addr_conflict_resolution = "dont_care")) generate
OR g_addr_conflict_resolution = "dont_care")) generate
port_a : process
begin
while (stop = FALSE) loop
......@@ -305,7 +305,7 @@ begin
end loop;
wait;
end process;
port_b : process
begin
while (stop = FALSE) loop
......@@ -323,10 +323,10 @@ begin
--------------------------------------------------------------------------------
-- Test case 3 : No byte enable & Write first in addr conflict resolution --
--------------------------------------------------------------------------------
g_no_byte_enable_write_first : if (g_with_byte_enable = FALSE
AND g_addr_conflict_resolution = "write_first") generate
port_a : process
begin
while (stop = FALSE) loop
......@@ -340,7 +340,7 @@ begin
end loop;
wait;
end process;
port_b : process
begin
while (stop = FALSE) loop
......@@ -354,16 +354,16 @@ begin
end loop;
wait;
end process;
end generate;
--------------------------------------------------------------------------------
-- Test case 4 : No byte enable & no change in addr conflict resolution --
--------------------------------------------------------------------------------
g_no_byte_enable_write_no_change : if (g_with_byte_enable = FALSE
AND g_addr_conflict_resolution = "no_change") generate
port_a : process
begin
while (stop = FALSE) loop
......@@ -376,7 +376,7 @@ begin
end loop;
wait;
end process;
port_b : process
begin
while (stop = FALSE) loop
......@@ -389,13 +389,13 @@ begin
end loop;
wait;
end process;
end generate;
--------------------------------------------------------------------------------
-- Assertions --
--------------------------------------------------------------------------------
-- Compare the testbench's RAM_A with the RTL output for port A
check_port_a : process(tb_clka_i)
begin
......
testbench/genrams/xilinx/generic_dpram_split/tb_generic_dpram_split.vhd
View file @ 044a3bb2
......@@ -89,7 +89,7 @@ architecture tb of tb_generic_dpram_split is
signal web_rep : std_logic_vector(c_num_bytes-1 downto 0) := (others=>'0');
signal s_int_a : natural;
signal s_int_b : natural;
-- Type of the RAM
type t_split_ram is array(0 to g_size-1) of std_logic_vector(7 downto 0);
......@@ -119,10 +119,10 @@ architecture tb of tb_generic_dpram_split is
f_file_to_ramtype(1),
f_file_to_ramtype(2),
f_file_to_ramtype(3));
begin
-- Unit Under Test
UUT : entity work.generic_dpram_split
generic map (
......@@ -145,16 +145,16 @@ begin
qb_o => tb_qb_o);
-- Clock and reset
clk_proc : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
clk_proc : process
begin
while stop = FALSE loop
tb_clk_i <= '1';
wait for C_CLK_PERIOD/2;
tb_clk_i <= '0';
wait for C_CLK_PERIOD/2;
end loop;
wait;
end process clk_proc;
tb_rst_n_i <= '0', '1' after 2 * C_CLK_PERIOD;
......@@ -199,7 +199,7 @@ begin
-- Processes to create two RAMs to store the data
ram_port_a_and_b : for i in 0 to 3 generate
port_a : process(tb_clk_i)
begin
if (rising_edge(tb_clk_I)) then
......@@ -240,7 +240,7 @@ begin
end if;
end if;
end process;
-- Compare the testbench's RAM_B with the RTL output for port B
check_port_b : process(tb_clk_i)
begin
......
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