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Platform-independent core collection
Commit 0352a53d authored by li hongming's avatar li hongming
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add dac_sel for gc_serial_dac.vhd

parent f73bc3d2
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Showing with 30 additions and 2 deletions
modules/common/gc_serial_dac.vhd
View file @ 0352a53d
...@@ -76,6 +76,7 @@ entity gc_serial_dac is ...@@ -76,6 +76,7 @@ entity gc_serial_dac is
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0); dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic; dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic; dac_sdata_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
-- when 1, the SPI interface is busy sending data to the DAC. -- when 1, the SPI interface is busy sending data to the DAC.
busy_o : out std_logic busy_o : out std_logic
...@@ -96,6 +97,8 @@ architecture syn of gc_serial_dac is ...@@ -96,6 +97,8 @@ architecture syn of gc_serial_dac is
signal divider_muxed : std_logic; signal divider_muxed : std_logic;
signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0); signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
signal dac_sel : std_logic_vector(2 downto 0);
begin begin
...@@ -167,6 +170,13 @@ begin ...@@ -167,6 +170,13 @@ begin
end if; end if;
end process; end process;
process(clk_i)
begin
if rising_edge(clk_i) then
dac_sel <= dac_sel_i;
end if;
end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
...@@ -175,8 +185,14 @@ begin ...@@ -175,8 +185,14 @@ begin
else else
if iValidValue = '1' and sendingData = '0' then if iValidValue = '1' and sendingData = '0' then
cs_sel_reg <= cs_sel_i; cs_sel_reg <= cs_sel_i;
dataSh(g_num_data_bits-1 downto 0) <= value_i; if(dac_sel = b"111") then
dataSh(dataSh'left downto g_num_data_bits) <= (others => '0'); dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
else
dataSh(dataSh'left downto g_num_data_bits+4)<= "0011";
dataSh(g_num_data_bits+4-1 downto 4) <= value_i;
dataSh(3 downto 0) <= (others => '0');
end if;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left); dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0); dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
......
modules/common/gencores_pkg.vhd
View file @ 0352a53d
...@@ -159,6 +159,7 @@ package gencores_pkg is ...@@ -159,6 +159,7 @@ package gencores_pkg is
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0); cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic; load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0); sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_sel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0); dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic; dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic; dac_sdata_o : out std_logic;
...@@ -657,6 +658,17 @@ package gencores_pkg is ...@@ -657,6 +658,17 @@ package gencores_pkg is
counter_o : out std_logic_vector(g_bits downto 0)); counter_o : out std_logic_vector(g_bits downto 0));
end component gc_async_counter_diff; end component gc_async_counter_diff;
component gc_dec_8b10b
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
in_10b_i : in std_logic_vector(9 downto 0);
ctrl_o : out std_logic;
code_err_o : out std_logic;
rdisp_err_o : out std_logic;
out_8b_o : out std_logic_vector(7 downto 0));
end component;
--============================================================================ --============================================================================
-- Procedures and functions -- Procedures and functions
--============================================================================ --============================================================================
......
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