add dac_sel for gc_serial_dac.vhd

0352a53d · li hongming · f73bc3d2 · 0352a53d · 0352a53d
Commit 0352a53d authored Jun 10, 2023 by li hongming
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Showing with 30 additions and 2 deletions

gc_serial_dac.vhd modules/common/gc_serial_dac.vhd +18 -2

gencores_pkg.vhd modules/common/gencores_pkg.vhd +12 -0

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--- a/modules/common/gc_serial_dac.vhd
+++ b/modules/common/gc_serial_dac.vhd
@@ -76,6 +76,7 @@ entity gc_serial_dac is
    dac_cs_n_o  : out std_logic_vector(g_num_cs_select-1 downto 0);
    dac_sclk_o  : out std_logic;
    dac_sdata_o : out std_logic;
+    dac_sel_i   : in  std_logic_vector(2 downto 0);

 -- when 1, the SPI interface is busy sending data to the DAC.
    busy_o : out std_logic
@@ -96,6 +97,8 @@ architecture syn of gc_serial_dac is
  signal divider_muxed : std_logic;

  signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
+
+  signal dac_sel  : std_logic_vector(2 downto 0);
  
 begin

@@ -167,6 +170,13 @@ begin
    end if;
  end process;

+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      dac_sel <= dac_sel_i;
+    end if;
+  end process;
+
  process(clk_i)
  begin
    if rising_edge(clk_i) then
@@ -175,8 +185,14 @@ begin
      else
        if iValidValue = '1' and sendingData = '0' then
          cs_sel_reg                                 <= cs_sel_i;
-          dataSh(g_num_data_bits-1 downto 0)         <= value_i;
-          dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
+          if(dac_sel = b"111") then
+            dataSh(g_num_data_bits-1 downto 0)         <= value_i;
+            dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
+          else
+            dataSh(dataSh'left downto g_num_data_bits+4)<= "0011";
+            dataSh(g_num_data_bits+4-1 downto 4)        <= value_i;
+            dataSh(3 downto 0)                          <= (others => '0');
+          end if;
        elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
          dataSh(0)                    <= dataSh(dataSh'left);
          dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);

--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -159,6 +159,7 @@ package gencores_pkg is
      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
      load_i        : in  std_logic;
      sclk_divsel_i : in  std_logic_vector(2 downto 0);
+      dac_sel_i     : in  std_logic_vector(2 downto 0);
      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
      dac_sclk_o    : out std_logic;
      dac_sdata_o   : out std_logic;
@@ -657,6 +658,17 @@ package gencores_pkg is
      counter_o : out std_logic_vector(g_bits downto 0));
  end component gc_async_counter_diff;

+  component gc_dec_8b10b
+    port (
+      clk_i       : in  std_logic;
+      rst_n_i     : in  std_logic;
+      in_10b_i    : in  std_logic_vector(9 downto 0);
+      ctrl_o      : out std_logic;
+      code_err_o  : out std_logic;
+      rdisp_err_o : out std_logic;
+      out_8b_o    : out std_logic_vector(7 downto 0));
+  end component;
+
  --============================================================================
  -- Procedures and functions
  --============================================================================