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Created with Raphaël 2.2.010Oct27Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May2711432common: add missing gc_delay_line.vhd. See also issue #1672sim: import and update bicolor LED controller testbench from SVEC projectxwb_lm32: don't include wr_node/mockturtle profile in the VHDL wrapperwb_axi4lite_bridge: now conforms to AXI4 standardgenrams/xilinx: remove optimizations for ram initializationMerge branch 'greg-vivado' into proposed_masteradding wb to axi4lite bridge by Tomgenrams: ram initialization functions should be impurelm32: fix strip_undefined function for Vivadowb_uart: regenerate wb interface with latest wbgencommon/gc_sync_ffs: add synchronizer attribute for Vivadogenrams/xilinx: speedup RAM initialization for most common widths (mainly for Vivado)genrams/xilinx: split ports to separate processes for Vivado synthesiswb_lm32: remove non synthesizable code when generating lm32_allprofiles.vcommon: added 8b10b decoder coreadding wb to axi4lite bridge by Tomgenrams: ram initialization functions should be impurelm32: fix strip_undefined function for Vivadowb_uart: regenerate wb interface with latest wbgencommon/gc_sync_ffs: add synchronizer attribute for Vivadogenrams/xilinx: speedup RAM initialization for most common widths (mainly for Vivado)genrams/xilinx: split ports to separate processes for Vivado synthesiswb_lm32: remove non synthesizable code when generating lm32_allprofiles.vinferred_sync_fifo: bugfix of almost_full/emptywrpc-v4.1wrpc-v4.1generic_shiftreg_fifo: assert almost_full_o one cycle in advancewb_pcie: increased size of clk crossing bufferMerge remote-tracking branch 'origin/eva-ds182x' into tom-proposed-master-feb27masterFIP_v1.1.0masterFIP_v1.1.0Merge remote-tracking branch 'origin/tom-mock-turtle' into proposed_masterMerge branch 'greg_ram_init' into proposed_masterwrpc-v4.0wrpc-v4.0increased address range of the cc_dummy_sdb_devicewb_dpram: no need to split into 4 BRAMs with generic_dpram_split inside generic_dpramgenrams: instantiate splitram in generic_dpramgenrams: move f_check_bounds to the packagegenrams/dpram: split dpram also when initializedgenrams: simplify RAM initialization during synthesisadded gc_dyn_extend_pulse.vhd where the width of the extended pulse comes as an input rather than a generic.minor improvements to reduce number of warnings generated by some of the coresxwb_lm32: expose all PC values for tracinghdl: added modification noticesdoc: added copy of original documentation for wb_spi and wb_onewire_master