gc_sync_word_rd has incorrect reset CDC

The p_writer process incorrectly uses rst_in_n_i reset from IN clock domain while it's driving signals in OUT domain:

  p_writer : process (clk_out_i)
  begin
    if rising_edge(clk_out_i) then
      if rst_in_n_i = '0' then -- shouldn't this be from OUT domain?
        ack_out_o <= '0';
      elsif wr_in = '1' then
        --  Data is stable.
        data_out_o <= gc_sync_word_data;
        ack_out_o    <= '1';
      else
        ack_out_o <= '0';
      end if;
    end if;
  end process;

This causes a CDC issue for ack_out flag and data_out_o port.
Unfortunately, this coding style will cause the CE pins of data_out_o registers to be driven by rst_in_n_i.