this is needed for VXS integration in which hdlmake is used to generate
a list of files used, these failes are alter copied to a Visual Elite
based project

hdl: add RLOC constraint to gc_sync_ffs in order to keep the two FFs as close as possible to each other

genram: automatically pad with zeroes when reading from a mem init file smaller than the memory itself

Apologies for the double renaming, but it occured to me that the constant names were too generic and could cause conflicts.

This is introduced to better match the OHWR VHDL coding style [1].

Old names are preserved for backward compatibility.

[1]: https://www.ohwr.org/projects/vhdl-style

For the few peripherals where it was being used (eg. uart, spi, etc) the output port
has been renamed to "int_o".

The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
by wbgen, and it would require users to update their wbgen tool as well. So, until a new
tool is introduced, wbgen-generated interrupt controllers will have an output port called
wb_int_o".