Commits · af71ba17599955879c7f216f907c5c64e2e8dd70 · Projects / Platform-independent core collection · GitLab

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Mar 01, 2013
- altera rams: use a default initial value of '0' to avoid hundreds of warnings · af71ba17
  Wesley W. Terpstra authored 12 years ago
  
  af71ba17
Mar 28, 2012
- genrams: fixed wrong bwsel port size when data width is not a multiple of 8 · b5c3f067
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
  
  b5c3f067
- modules/genrams: Added genrams library (initial commit) · fbac4470
  Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.
```
  fbac4470
Oct 25, 2011
- genrams: fixed bwsel size bug · 4f870cde
  Tomasz Wlostowski authored 13 years ago
  
  4f870cde
May 02, 2011
- added genrams · 731acd76
  Tomasz Wlostowski authored 13 years ago
  
  731acd76