Bug: std_match is needed when comparing '-'s

stub wishbone device added for testing

Implement a wishbone streaming interface bridge from the Avalon RX stream

Add driver stub code

Modified PLL for two outputs
Added power on reset
Re-instantiated the PCIe megafunction

I have no idea why.

With 63, no dual port memory is inferred.
With 7, it all works peachy.

Why on earth it affects completely independent code I cannot explain.

Conflicts:
	modules/common/Manifest.py
	modules/common/gencores_pkg.vhd
	modules/genrams/Manifest.py
	modules/genrams/altera/generic_dpram.vhd
	modules/genrams/genram_pkg.vhd
	modules/genrams/memory_loader_pkg.vhd
	modules/genrams/xilinx/Manifest.py
	modules/genrams/xilinx/generic_dpram.vhd
	modules/wishbone/Manifest.py
	modules/wishbone/wb_crossbar/Manifest.py
	modules/wishbone/wb_crossbar/xwb_crossbar.vhd
	modules/wishbone/wb_dpram/xwb_dpram.vhd
	modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
	modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
	modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
	modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
	modules/wishbone/wbgen2/wbgen2_pkg.vhd
	modules/wishbone/wishbone_pkg.vhd

genrams/xilinx/generic_dpram: made two separate versions for memories with both ports clocked with the same signal and with independent clocks

This is to prevent ISE from interpreting the single-clock template as a dual-clock one, which may result in read-after-write memory content corruption on Spartan-6/Virtex-6 FPGAs.

modules/wishbone/wb_onewire_master: added 1-cycle ack delay (fixes pipelined->classic conversion issues and greatly improves timing)

modules/wishbone/wb_slave_adapter: WE should also be latched when converting from PIPELINED to CLASSIC mode

genrams: increased width of internal byte select array to avoid compilation/synthesis errors on rams wider than 64 bits