For the few peripherals where it was being used (eg. uart, spi, etc) the output port
has been renamed to "int_o".

The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
by wbgen, and it would require users to update their wbgen tool as well. So, until a new
tool is introduced, wbgen-generated interrupt controllers will have an output port called
wb_int_o".

The RW ordering on address conflict varies by platform.
Some platforms only support some options.
Most of the dprams in WR are portable and don't depend on the order.
This new option allows a core to specify that it does not care what
the result of a RW conflict is, and thus work on more platforms.

For Xilinx, "dont_care" = "read_first", the old default.

In the past we used a generic to set the initial memory contents on altera.
Unfortunately, quartus compiles big generics slowly (read: hours).
Now we can load from a .mif file instead, which is much faster (seconds).
Thus, this old option is no longer needed.

Quartus will not process a 'file_open' call during synthesis,
so we can instead initialize the RAM with a vhdl constant.