added gc_dyn_extend_pulse.vhd where the width of the extended pulse comes as an input rather than a generic.

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

common/gc_i2c_slave: added option to allow automatic ACK of address byte without external user intervention

gc_frequency_meter: use gc_pulse_synchronizer for external PPS pulse (in case the measured frequency is slower than the gating frequency)

Lucas Russo authored 8 years ago and Maciej Lipinski committed 8 years ago

Signed-off-by: Maciej Lipinski <maciej.lipinski@cern.ch>

It seems that similar modules might be needed in other designs. The
added gc_async_signals_input_stage provides:
- synchronisation of input digital asynchronous pulses with the clock
- degliching (filter len config through generic)
- single-clock pulse generation
- extended pulses generation (config through generic)

The new gc_single_reset_gen can generate a single reset signal that
is synchronous with the system clock domain (input clk). The input
to the module is a vector of asynchronous reset signals, such as
PCIe reset or button. These input signals are synchronised with
the clock domain. Additionally, the powerup count-down is taken care
for by the module. The resulting single reset signal is passed through
a programmable number of flip-flops at the output (g_out_reg_depth)
so that the ISE optimizer has easier work with the global reset
funout.

This module is a generalized and (hopefully) improved version of the
spec_reset_gen.vhd that is copy+pasted into many SPEC-based designed.
It was suggested during a review of one of such designes that this
reset should be added to general-cores. This is the execution of this
feedback.

This module might be potentially integrated with the other available
reset-generation module (gc_reset.vhd).

gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;