Skip to content
Snippets Groups Projects
  1. May 02, 2017
  2. Mar 16, 2017
  3. Feb 20, 2017
  4. Feb 14, 2017
  5. Feb 03, 2017
  6. Dec 15, 2016
  7. Nov 29, 2016
  8. Nov 28, 2016
  9. Nov 23, 2016
  10. Nov 17, 2016
  11. Oct 27, 2016
  12. Oct 17, 2016
  13. Oct 05, 2016
  14. Sep 27, 2016
  15. Aug 30, 2016
  16. Aug 25, 2016
    • Maciej Lipinski's avatar
      The added module is used in the SPEC-based WR-Btrain transmitter design. · 4100df70
      Maciej Lipinski authored
      It seems that similar modules might be needed in other designs. The
      added gc_async_signals_input_stage provides:
      - synchronisation of input digital asynchronous pulses with the clock
      - degliching (filter len config through generic)
      - single-clock pulse generation
      - extended pulses generation (config through generic)
      4100df70