hdl: added assignments to (new) unspecified WB signals

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd

@@ -213,4 +213,5 @@ begin
       end if;
    end process;
 
+   slave_o.int <= '0'; -- TODO: not implemented
 end rtl;

modules/wishbone/wb_i2c_master/wb_i2c_master.vhd

@@ -149,6 +149,9 @@ begin
   wb_out.dat(7 downto 0)                <= dat_out;
   wb_out.dat(wb_out.dat'left downto 8) <= (others => '0');
 
+  wb_out.err <= '0';
+  wb_out.rty <= '0';
+  wb_out.stall <= '0';
 
 end rtl;
 

modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd

@@ -80,5 +80,8 @@ begin  -- rtl
       sda_pad_i    => sda_pad_i,
       sda_pad_o    => sda_pad_o,
       sda_padoen_o => sda_padoen_o);
+  
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
 end rtl;
 

modules/wishbone/wb_spi/wb_spi.vhd

@@ -127,4 +127,7 @@ begin
       mosi_pad_o => pad_mosi_o,
       miso_pad_i => pad_miso_i);
 
+    wb_out.rty <= '0';
+    wb_out.stall <= '0';
+
 end rtl;

modules/wishbone/wb_spi/xwb_spi.vhd

@@ -85,5 +85,7 @@ begin
       pad_sclk_o => pad_sclk_o,
       pad_mosi_o => pad_mosi_o,
       pad_miso_i => pad_miso_i);
+
+  slave_o.rty <= '0';
   
 end rtl;