hdl: added assignments to (new) unspecified WB signals
Signed-off-by:
Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
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- modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd 1 addition, 0 deletionsmodules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
- modules/wishbone/wb_i2c_master/wb_i2c_master.vhd 3 additions, 0 deletionsmodules/wishbone/wb_i2c_master/wb_i2c_master.vhd
- modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd 3 additions, 0 deletionsmodules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
- modules/wishbone/wb_spi/wb_spi.vhd 3 additions, 0 deletionsmodules/wishbone/wb_spi/wb_spi.vhd
- modules/wishbone/wb_spi/xwb_spi.vhd 2 additions, 0 deletionsmodules/wishbone/wb_spi/xwb_spi.vhd
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