Commits · 3e30ebb45be301410412f0849c7a4555b8f8d5ea · Projects / Platform-independent core collection · GitLab

Snippets Groups Projects

Mar 02, 2012
- Re-apply the SDWB patches against a known good point · 3e30ebb4
  Wesley W. Terpstra authored 13 years ago
  
  3e30ebb4
Feb 09, 2012
- wishbone/wb_lm32: fixed typo in (I/D)cache burst length causing lockup if I-cache was enabled · 26a43bc3
  Tomasz Wlostowski authored 13 years ago
  
  26a43bc3
Jan 31, 2012
- testbench/wishbone: added testbench for wb_xilinx_fpga_loader · a110631c
  Tomasz Wlostowski authored 13 years ago
  
  a110631c
- sim: uploaded Wishbone BFMs · b3505080
  Tomasz Wlostowski authored 13 years ago
  
  b3505080
- common/gencores_pkg: added round-robin arbitration function · e2fafbbc
  Tomasz Wlostowski authored 13 years ago
  
  e2fafbbc
- wishbone: added Xilinx FPGA serial loader (wb_xilinx_fpga_loader) · 2e5c4532
  Tomasz Wlostowski authored 13 years ago
  
  2e5c4532
- wishbone/wb_slave_adapter: checks stall line only in PIPELINED mode · a9be15e6
  Tomasz Wlostowski authored 13 years ago
  
  a9be15e6
Jan 24, 2012
- genrams/xilinx/generic_dpram.vhd: removed clock assignemnts (simulation issues) · 4e1e6fb5
  Tomasz Wlostowski authored 13 years ago
  
  4e1e6fb5
- genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused... · 7518aee8
  Tomasz Wlostowski authored 13 years ago
```
genrams: genram_pkg.vhd: added f_gen_dummy_vec() function, padded unused inputs of RAMs/FIFOs to default values
```
  7518aee8
- genrams: generic_shiftreg_fifo.vhd: added zero-ing on reset · 718b882d
  Tomasz Wlostowski authored 13 years ago
  
  718b882d
Jan 17, 2012
- updated .gitignore · 1747826c
  Tomasz Wlostowski authored 13 years ago
  
  1747826c
- genrams: changed empty port in generic_shiftreg_fifo to q_valid (it's a show-ahead FIFO) · 2fe883a2
  Tomasz Wlostowski authored 13 years ago
  
  2fe883a2
- wishbone/wb_lm32: fixed wrong path in manifest · 775bcb71
  Tomasz Wlostowski authored 13 years ago
  
  775bcb71
Jan 16, 2012
- wishbone: added wb_vic components to wishbone_pkg · 247ca5e8
  Tomasz Wlostowski authored 13 years ago
  
  247ca5e8
- modules/wb_vic: fixed port names to match the coding style · 8e81b8b1
  Tomasz Wlostowski authored 13 years ago
  
  8e81b8b1
- wishbone/wb_slave_adapter: fixed pipelined->classic conversion missing acks bug · da28313f
  Tomasz Wlostowski authored 13 years ago
  
  da28313f
- wishbone/wb_lm32: now uses generic multiplier for FPGAs other than Spartan6 to avoid mapping errors · 5eaa5033
  Tomasz Wlostowski authored 13 years ago
  
  5eaa5033
- genrams: added small synchronous shift register-based FIFO (generic_shiftreg_fifo) · 541e36c1
  Tomasz Wlostowski authored 13 years ago
  
  541e36c1
- genrams: now distinguishes between FIFOs for Virtex6/Spartan6 · 9124e68a
  Tomasz Wlostowski authored 13 years ago
  
  9124e68a
- modules/common: updated manifest and package with freshly added modules · 2a321348
  Tomasz Wlostowski authored 13 years ago
  
  2a321348
- modules/common: added frequency meter (gc_frequency_meter) · 68b98ba9
  Tomasz Wlostowski authored 13 years ago
  
  68b98ba9
- modules/common: added clock rate independent pulse synchronizer (gc_pulse_synchronizer) · f6250338
  Tomasz Wlostowski authored 13 years ago
  
  f6250338
Nov 04, 2011
- Document the timing and area costs of the crossbar. · 96e71e67
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  96e71e67
- Improve timings: Make all MUXs explicitly log deep Add a Kogge-Stone OR... · 4c72d449
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Improve timings: Make all MUXs explicitly log deep Add a Kogge-Stone OR network for arbitration (makes arbitration scale log(n) with n masters, not O(n))

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  4c72d449
Nov 02, 2011
- wishbone/wb_slave_adapter: prevents a pipelined master from chaging data/addr... · 2427a12c
  Tomasz Wlostowski authored 13 years ago
```
wishbone/wb_slave_adapter: prevents a pipelined master from chaging data/addr lines when talking to classic slave
```
  2427a12c
- wishbone/xwb_bus_fanout: now determines the number of peripheral select bits... · 601de57a
  Tomasz Wlostowski authored 13 years ago
```
wishbone/xwb_bus_fanout: now determines the number of peripheral select bits from number of connected peripherals
```
  601de57a
- genrams: wea_i/web_i must not be ignored in byte addressed mode · 2f4143b0
  Tomasz Wlostowski authored 13 years ago
  
  2f4143b0
- Refactor the variable names · 8f48feb3
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  8f48feb3
- It is now possible to much more clearly state how async and sync differ. · 60206e72
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  60206e72
- Remove all the special-case code dealing with errors. It was hard to reason about, timing-wise. · 8ec84d06
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Make the error device a completely standard wishbone device;
we don't need high performance segfaults. Clearer is better.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  8ec84d06
- Detect when there is a bus error. · 6b340010
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  6b340010
- The stack was overflowing the size of the wired dp ram. · c91a49e4
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  c91a49e4
- The actual bugfix for registered crossbar timings. · 2d2f5265
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
This bug allowed a high priority master to seize control of a lower priority master if:
1. The low priority master had control for exactly one cycle
2. Combinatorial crossbar mode was off

... this made it possible to "steal the ACK" of another device and cause the bus to stall.

This commit will be followed by a few others which also tidy up the code a
bit in a way that would have made this bug more obvious to a reviewer.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  2d2f5265
- depth != width. Overflow of integer size => register file uncleared. · 31538117
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  31538117
- It is much easier to trace the workings of the crossbar if you can see the granted pins! · 8b2dc1e3
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  8b2dc1e3
- xwb_simple_uart: must tie ERR, RTY & INT lines to zero when not used · 6934e72f
  Tomasz Wlostowski authored 13 years ago
  
  6934e72f
- Modelsim requires all wires explicitly declared. · 824a460b
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  824a460b
- updated lm32_testsys testbench · c8dc1989
  Tomasz Wlostowski authored 13 years ago
  
  c8dc1989
Nov 01, 2011
- genrams: removed extra delays on clock lines for simulation · 28382b30
  Tomasz Wlostowski authored 13 years ago
  
  28382b30
- genrams: disabled messages in memory_loader_pkg · 58959bc6
  Tomasz Wlostowski authored 13 years ago
  
  58959bc6