The subrange type might not be known in this context.
Fixes:
  wishbone_pkg.vhd:1379:26: object subtype is not locally static

Variable lengths might change; standard forbids length in a loop.
Fixes:
  wishbone_pkg.vhd:1576:18: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1613:18: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1734:30: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1771:16: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1806:16: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1817:16: universal integer bound must be numeric literal or attribute

Sometimes a master needs to stop the flow of acks.

Now wb_spi has generic parameters to configure registers length and number of
spi slaves. Reason for that is to keep default configuration in the repository
but also allow to adjust settings for WR Switch synthesis (and save resources).

The values used in WR Switch software fit in 8-bit registers so using 16-bits
in HDL was waste of resources.

Commit adds new WB register(IFS) that selects to which I2C interface master
should talk to. All other interfaces are then hold in idle state. IFS contains
also BUSY bit that is written only by host and marks that I2C Master is
currently in use and cannot be switched to another I2C interface. Host must
clear BUSY flag after the interaction with I2C interface is finished.

This is done to better reflect the interface of the module (structured Wishbone).
The documentation of the module is also changed in this respect.

It was causing the simulation to fail with designs containing a xwb_register_link component.

the sdb address of the wb crossbar. The sdb address
is store in a CSR, 0xb, and it can be retrieved from the
firmware using an asm macro call.

Using the volatile configuration register to configure a flash chip
is a bad idea. The problem is that if the FPGA is reset, the flash
may be in a state inconsistent with what the FPGA requires to boot.

The correct solution is to configure the non-volatile configuration
register on the chip to what the FPGA expects on power-on. Then use
these same settings inside the flash core.

Going this route makes it necessary for software to be able to set
the non-volatile configuration register. Rather than making the core
even more complicated than it is, I have elected to add a FIFO which
software can fill to issue custom SPI commands. Since erase can only
be done from software anyway, I removed this code and let erase use
the custom command FIFO.

This is done by adding a generic to the entity, which is connected directly to
the gc_fsm_watchdog component instantiated within the wb_i2c_bridge. The user
should calculate the appropriate watchdog timeout value and set it via this
generic.

The instantiation template in the wishbone_pkg is also updated.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Miguel Jimenez Lopez authored 11 years ago and Grzegorz Daniluk committed 11 years ago

This change is necessary for network control/monitor tool in order to read the GUI command output.
The GUI command output can not be stored into a 1024 bytes fifo.

wb_irq_slave: added clear and enable registers

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- I2C slave component now samples SDA line one rising SCL and changes
states and shifts out bits on its falling edge
- I2C slave component has clearer status outputs
- bridge component changed to reflect changes in I2C slave interface
- bridge component also returns to IDLE state on I2C stop condition, as
reflected by the I2C slave

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- gc_i2c_slave     -- generic I2C slave to be used with a processor or tied to a
                      Wishbone interface
- gc_glitch_filter -- glitch filter with selectable number of taps
- wb_i2c_bridge    -- I2C bridge implementing the protocol defined with ELMA
                      for monitoring VME crates
- wb_xil_multiboot -- module that accesses the Spartan-6 configuration logic
                      for reconfiguring the FPGA using MultiBoot

Doc files for each of these modules can be found in the doc/ folder.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

c_status_time was one cycle longer than it should be!
this led to the arria5 requiring g_dummy_time-1 in c_vstatus_data
==> after fixing: must increase g_input_to_output_cycles on arria5

there was also a wrong calculation for s_wip with single-lane mode
it was working also by luck because WEL and WIP are usually set
together and are side-by-side, thus masking the c_status_time bug.