Commits · 1e91b2391bf4ce6a58d8ae10c4b9308c950b2f0a · Projects / Platform-independent core collection · GitLab

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Dec 13, 2017
- no technical change, cleanup copyright holders · 1e91b239
  Grzegorz Daniluk authored 7 years ago
  
  1e91b239
Oct 11, 2017
- wishbone/wb_gpio_port: add simple testbench · ec002a60
  Dimitris Lampridis authored 7 years ago
  
  ec002a60
- wishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is... · 34738f83
  Dimitris Lampridis authored 7 years ago
```
wishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is not an exact multiple of 32. Closes #1532
```
  34738f83
- common: add default value to master reset in gc_reset. Closes #1628 · e7c18e57
  Dimitris Lampridis authored 7 years ago
  
  e7c18e57
- sim: add simple testbench for gc_moving_average · eb988d11
  Dimitris Lampridis authored 7 years ago
  
  eb988d11
- common: cleanup gc_moving_average, remove unused signals and ports, drive dout_stb_o · a12e49df
  Dimitris Lampridis authored 7 years ago
  
  a12e49df
- common: add init values to signals in gc_delay_line to prevent sim warnings · e892fccf
  Dimitris Lampridis authored 7 years ago
  
  e892fccf
- common: add gc_delay_line to Manifest and package · 0467f2bf
  Dimitris Lampridis authored 7 years ago
  
  0467f2bf
- genrams: make function specifications conform to function bodies · ebb5bbef
  Dimitris Lampridis authored 7 years ago
  
  ebb5bbef
- common: fix component declaration for gc_moving_average · f9f3bc22
  Dimitris Lampridis authored 7 years ago
  
  f9f3bc22
Oct 10, 2017
- common: add missing gc_delay_line.vhd. See also issue #1672 · a259e5c6
  Dimitris Lampridis authored 7 years ago
  
  a259e5c6
Sep 27, 2017
- sim: import and update bicolor LED controller testbench from SVEC project · 02a5a17b
  Dimitris Lampridis authored 7 years ago
  
  02a5a17b
Aug 25, 2017
- genrams/xilinx: remove optimizations for ram initialization · 338eeed9
  Grzegorz Daniluk authored 7 years ago
```
They finally don't help much and they break simulation as Modelsim complains
about types conversion.
```
  338eeed9
- Merge branch 'greg-vivado' into proposed_master · ab1ee585
  Grzegorz Daniluk authored 7 years ago
  
  ab1ee585
- adding wb to axi4lite bridge by Tom · 6016433a
  Grzegorz Daniluk authored 7 years ago
  
  6016433a
- genrams: ram initialization functions should be impure · 53cfac24
  Grzegorz Daniluk authored 7 years ago
  
  53cfac24
- lm32: fix strip_undefined function for Vivado · c590dfac
  Grzegorz Daniluk authored 7 years ago
```
Fix it the same way as f_x_to_zero() is fixed in wbgen.
```
  c590dfac
- wb_uart: regenerate wb interface with latest wbgen · 36f62c0a
  Grzegorz Daniluk authored 7 years ago
```
It fixes some functions not well understood by Vivado synthesis
```
  36f62c0a
- common/gc_sync_ffs: add synchronizer attribute for Vivado · 1321f531
  Grzegorz Daniluk authored 7 years ago
  
  1321f531
- genrams/xilinx: speedup RAM initialization for most common widths (mainly for Vivado) · ec5fe1ce
  Grzegorz Daniluk authored 7 years ago
  
  ec5fe1ce
- genrams/xilinx: split ports to separate processes for Vivado synthesis · 3833555a
  Grzegorz Daniluk authored 7 years ago
  
  3833555a
- wb_lm32: remove non synthesizable code when generating lm32_allprofiles.v · f4c0344a
  Grzegorz Daniluk authored 7 years ago
  
  f4c0344a
Aug 22, 2017
- common: added 8b10b decoder core · 47b5fcb2
  Tomasz Wlostowski authored 7 years ago
  
  47b5fcb2
Jun 23, 2017
- inferred_sync_fifo: bugfix of almost_full/empty · 96295346
  Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago
```
it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.
```
  wrpc-v4.1
  
  96295346
May 02, 2017
- generic_shiftreg_fifo: assert almost_full_o one cycle in advance · 6db1d955
  Tomasz Wlostowski authored 8 years ago
  
  6db1d955
Mar 16, 2017
- wb_pcie: increased size of clk crossing buffer · 9cc9792e
  Stefan Rauch authored 8 years ago
  
  9cc9792e
Feb 20, 2017
- Merge branch 'greg_ram_init' into proposed_master · c0614a39
  Grzegorz Daniluk authored 8 years ago
  
  wrpc-v4.0
  
  c0614a39
Feb 14, 2017
- wb_dpram: no need to split into 4 BRAMs with generic_dpram_split inside generic_dpram · 0973db51
  Grzegorz Daniluk authored 8 years ago
  
  0973db51
- genrams: instantiate splitram in generic_dpram · 2f75877d
  Grzegorz Daniluk authored 8 years ago
  
  2f75877d
- genrams: move f_check_bounds to the package · 21e552ef
  Grzegorz Daniluk authored 8 years ago
  
  21e552ef
- genrams/dpram: split dpram also when initialized · 2a38b2a8
  Grzegorz Daniluk authored 8 years ago
  
  2a38b2a8
- genrams: simplify RAM initialization during synthesis · c283c216
  Grzegorz Daniluk authored 8 years ago
```
New function expects textfile with binary representation of each word in a
separate line, e.g.:
10011000000000000000000000000000
11010000000000000000000000000000
11010000001000000000000000000000
01111000000000010000000000000000
00111000001000010000000000000000

This for example reduces WRPC SPEC reference design synthesis time from ~26
minutes to ~11 minutes.
```
  c283c216
Feb 03, 2017
- minor improvements to reduce number of warnings generated by some of the cores · b833b5d8
  Dimitris Lampridis authored 8 years ago
  
  b833b5d8
Dec 15, 2016
- hdl: added modification notices · 0d75c0fd
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  0d75c0fd
- doc: added copy of original documentation for wb_spi and wb_onewire_master · e745dc3b
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  e745dc3b
- wb_onewire_master: propagated CDR_N/O generics up the hierarchy; added... · d3575021
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
wb_onewire_master: propagated CDR_N/O generics up the hierarchy; added assignments to (new) unspecified WB signals

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  d3575021
- wb_onewire_master: added default values; typos · 73ae91e6
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  73ae91e6
- gc_sync_register: added ASYNC_REG attribute for better timing analysis/simulation in Xilinx tools · 7acfff5e
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  7acfff5e
- gc_serial_dac: removed synchronous reset from sensitivity lists · 8cc13a10
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  8cc13a10
- hdl: added assignments to (new) unspecified WB signals · bebe354f
  Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago
```
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
```
  bebe354f