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Created with Raphaël 2.2.08May6330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18onewire: fix synthesis warningsaltera dcfifo: synchronize read resetaltera dpram: quell modelsim warningxwb_dma: convert custom array to generic_simple_dpramxwb_dma: convert variables into signalsxwb_streamer: reduce to a wrapper of xwb_dmamodules/common/Manifest.py: remove gc_dual_clock_ram, it's no more in the repogc_extend_pulse: save some resources, don't need to use fixed size 32-bit counteraltera pcie: fix a race condition in the bar switchoverremove gc_wfifo in favour of generic_async_fifoaltera: add flash interfacespi_flash: add enough parameters to work around buggy altera spi timingsserial_lcd + spi_flash: missing copyrightsspi_flash: memory-mapped flash memory (can program an Altera FPGA)move platform specific modules into conditional foldersdma: support uncontrolled streaming between two slavesgenrams/generic_shiftreg_fifo.vhd: reset pointer when reset is assertedtestbench/wishbone: TB for wb_simple_pwmwishbone: updated wishbone package (PWM & new SDB descriptors), minor VHDL'93 compliance fixwishbone: added wb_simple_pwm PWM controllerwishbone_pkg: added SDB desriptors for I2C, 1-ie and SPI mastersdoc: initial (and incomplete) version of the manualwishbone/wb_vic: more verbose documentationcommon/gc_crc_gen: fixed reverse_range bug causing invalid CRCs, added restart input and combinatorial output to reduce latencycommon/gc_word_packer: uploaded missing source filewishbone_pkg: added SDB descriptor for xwb_vicgenrams/inferred_sync_fifo: assert full flag one cycle in advance[xilinx] genrams/v6_hwfifo_wrapper: parameter/signal validation to avoid DRC errorscommon/gc_crc_gen: generic byte swappingcommon: added gc_word_packer to manifest and packagewishbone/wb_xilinx_fpga_loader: testbench fixesgenrams/inferred_sync_fifo: fixed show ahead mode, keep output unchanged when rd_i = 0genrams/generic_shiftreg_fifo: force native SRL implementation on Xilinx devicesgenrams: removed dependency on Xilinx coregen, use native FIFO18/36 primitives on Virtex6common: improved RR arbiterserial_lcd: generic_dpram dual_clock generic matters now -- it was wronglm32: use generic_simple_dpram instead of custom memorygc_wfifo: eliminate custom memory; use generic_simple_dpram insteadaltera pcie: use generic_simple_dpram instead of custom memorygenrams: rewrote altera variants using altsyncram