gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;