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Commit 898be73f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wishbone: wb_slave_adapter: now asserts STB until ACKed in classic mode

parent 05296b35
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...@@ -169,25 +169,25 @@ begin -- rtl ...@@ -169,25 +169,25 @@ begin -- rtl
p_gen_control : process(slave_in, slave_out, master_in, master_out) p_gen_control : process(slave_in, slave_out, master_in, master_out)
begin begin
if(g_slave_mode = PIPELINED and g_master_mode = CLASSIC) then if(g_master_mode = PIPELINED and g_slave_mode = CLASSIC) then
if(fsm_state = IDLE) then if(fsm_state = IDLE) then
master_out.stb <= slave_in.stb; master_out.stb <= slave_in.stb;
else else
master_out.stb <= '0'; master_out.stb <= '0';
end if; end if;
slave_out.stall <= '0'; slave_out.stall <= '0';
elsif(g_slave_mode = CLASSIC and g_master_mode = PIPELINED) then elsif(g_master_mode = CLASSIC and g_slave_mode = PIPELINED) then
if(fsm_state = WAIT4ACK) then if(fsm_state = WAIT4ACK) then
master_out.stb <= '1'; master_out.stb <= '1';
else else
master_out.stb <= slave_in.stb; master_out.stb <= slave_in.stb;
end if; end if;
if(master_out.cyc = '1') then if(fsm_state = WAIT4ACK) then
slave_out.stall <= '0'; slave_out.stall <= not slave_out.ack;
else else
slave_out.stall <= not master_in.ack; slave_out.stall <= '0';
end if; end if;
else else
master_out.stb <= slave_in.stb; master_out.stb <= slave_in.stb;
......
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