fix almost_full threshold for Virtex6 FIFO

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources

modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd

@@ -127,6 +127,10 @@ architecture syn of generic_sync_fifo is
 
   constant m : t_v6_fifo_mapping := f_v6_fifo_find_mapping(g_data_width, g_size);
 
+  -- Xilinx defines almost full threshold as number of available empty words in
+  -- FIFO (UG363 - Virtex 6 FPGA Memory Resources
+  constant c_virtex_almost_full_thr : integer := g_size - g_almost_full_threshold;
+
 begin  -- syn
 
   gen_inferred : if(m.d_width = 0) generate
@@ -169,7 +173,7 @@ begin  -- syn
         g_size                   => g_size,
         g_dual_clock             => false,
         g_almost_empty_threshold => f_empty_thr(g_with_almost_empty, g_almost_empty_threshold, g_size),
-        g_almost_full_threshold  => f_empty_thr(g_with_almost_full, g_almost_full_threshold, g_size),
+        g_almost_full_threshold  => f_empty_thr(g_with_almost_full, c_virtex_almost_full_thr, g_size),
         g_with_count             => g_with_count)
       port map (
         rst_n_i           => rst_n_i,