hdl: update synchronizers and add attributes to help with placement of timing constraints

modules/common/gc_pulse_synchronizer.vhd

@@ -29,7 +29,7 @@ use ieee.std_logic_1164.all;
 use work.gencores_pkg.all;
 
 entity gc_pulse_synchronizer is
-  
+
   port (
     -- pulse input clock
     clk_in_i  : in  std_logic;
@@ -37,8 +37,8 @@ entity gc_pulse_synchronizer is
     clk_out_i : in  std_logic;
     -- system reset (clk_in_i domain)
     rst_n_i   : in  std_logic;
-    -- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-    -- correctly transferred to q_p_o.
+    -- pulse input ready (clk_in_i domain). When HI, a pulse
+    -- coming to d_p_i will be correctly transferred to q_p_o.
     d_ready_o : out std_logic;
     -- pulse input (clk_in_i domain)
     d_p_i     : in  std_logic;
@@ -49,40 +49,29 @@ end gc_pulse_synchronizer;
 
 architecture rtl of gc_pulse_synchronizer is
 
-  constant c_sync_stages : integer := 3;
-
-  signal ready, d_p_d0 : std_logic;
-
+  signal ready, d_p_d0   : std_logic;
   signal in_ext, out_ext : std_logic;
   signal out_feedback    : std_logic;
 
-  signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
-  signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
-
 begin  -- rtl
 
-  process(clk_out_i, rst_n_i)
-  begin
-    if rst_n_i = '0' then
-      d_in2out <= (others => '0');
-      out_ext <= '0';
-    elsif rising_edge(clk_out_i) then
-      d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
-      out_ext <= d_in2out(c_sync_stages-1);
-    end if;
-  end process;
-
-
-  process(clk_in_i, rst_n_i)
-  begin
-    if rst_n_i = '0' then
-      d_out2in <= (others => '0');
-    elsif rising_edge(clk_in_i) then
-      d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
-    end if;
-  end process;
-
-  out_feedback <= d_out2in(c_sync_stages-1);
+  cmp_in2out_sync : gc_sync_ffs
+    port map (
+      clk_i    => clk_out_i,
+      rst_n_i  => rst_n_i,
+      data_i   => in_ext,
+      synced_o => out_ext,
+      npulse_o => open,
+      ppulse_o => q_p_o);
+
+  cmp_out2in_sync : gc_sync_ffs
+    port map (
+      clk_i    => clk_in_i,
+      rst_n_i  => rst_n_i,
+      data_i   => out_ext,
+      synced_o => out_feedback,
+      npulse_o => open,
+      ppulse_o => open);
 
   p_input_ack : process(clk_in_i, rst_n_i)
   begin
@@ -93,26 +82,17 @@ begin  -- rtl
     elsif rising_edge(clk_in_i) then
 
       d_p_d0 <= d_p_i;
-      
-      if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
+
+      if ready = '1' and d_p_i = '1' and d_p_d0 = '0'then
         in_ext <= '1';
         ready  <= '0';
-      elsif(in_ext = '1' and out_feedback = '1') then
+      elsif in_ext = '1' and out_feedback = '1' then
         in_ext <= '0';
-      elsif(in_ext = '0' and out_feedback = '0') then
+      elsif in_ext = '0' and out_feedback = '0' then
         ready <= '1';
       end if;
     end if;
-  end process;
-
-  p_drive_output : process(clk_out_i, rst_n_i)
-  begin
-    if rst_n_i = '0' then
-      q_p_o <= '0';
-    elsif rising_edge(clk_out_i) then
-      q_p_o <= not out_ext and d_in2out(c_sync_stages-1);
-    end if;
-  end process;
+  end process p_input_ack;
 
   d_ready_o <= ready;
 

modules/common/gc_sync_ffs.vhd

@@ -47,6 +47,8 @@ end gc_sync_ffs;
 architecture behavioral of gc_sync_ffs is
   signal sync0, sync1, sync2 : std_logic;
 
+  signal gc_sync_ffs_in : std_logic;
+
   attribute shreg_extract : string;
   attribute shreg_extract of sync0  : signal is "no";
   attribute shreg_extract of sync1  : signal is "no";
@@ -56,6 +58,8 @@ architecture behavioral of gc_sync_ffs is
   attribute keep of sync0  : signal is "true";
   attribute keep of sync1  : signal is "true";
 
+  attribute keep of gc_sync_ffs_in : signal is "true";
+
   -- synchronizer attribute for Vivado
   attribute ASYNC_REG : string;
   attribute ASYNC_REG of sync0 : signal is "true";
@@ -64,6 +68,9 @@ architecture behavioral of gc_sync_ffs is
 
 begin
 
+  -- rename data_i to something we can use as wildcard
+  -- in timing constraints
+  gc_sync_ffs_in <= data_i;
 
   sync_posedge : if (g_sync_edge = "positive") generate
     process(clk_i, rst_n_i)
@@ -76,7 +83,7 @@ begin
         npulse_o <= '0';
         ppulse_o <= '0';
       elsif rising_edge(clk_i) then
-        sync0    <= data_i;
+        sync0    <= gc_sync_ffs_in;
         sync1    <= sync0;
         sync2    <= sync1;
         synced_o <= sync1;
@@ -97,7 +104,7 @@ begin
         npulse_o <= '0';
         ppulse_o <= '0';
       elsif falling_edge(clk_i) then
-        sync0    <= data_i;
+        sync0    <= gc_sync_ffs_in;
         sync1    <= sync0;
         sync2    <= sync1;
         synced_o <= sync1;
@@ -106,5 +113,5 @@ begin
       end if;
     end process;
   end generate sync_negedge;
-  
+
 end behavioral;