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  1. Jul 27, 2018
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  11. Mar 19, 2018
    • Dimitris Lampridis's avatar
      hdl: Eradicate INT from wishbone records and peripheral ports. · 61ca3f49
      Dimitris Lampridis authored
      For the few peripherals where it was being used (eg. uart, spi, etc) the output port
      has been renamed to "int_o".
      
      The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
      by wbgen, and it would require users to update their wbgen tool as well. So, until a new
      tool is introduced, wbgen-generated interrupt controllers will have an output port called
      wb_int_o".
      61ca3f49
  12. Mar 16, 2018
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  15. Mar 09, 2018
  16. Mar 08, 2018
    • Dimitris Lampridis's avatar
      hdl: fix typo in common Manifest · 8ad7b781
      Dimitris Lampridis authored
      8ad7b781
    • Theodor-Adrian Stana's avatar
      wb_i2c_bridge: Fix error in state-machine · 46e0f6dc
      Theodor-Adrian Stana authored and Dimitris Lampridis's avatar Dimitris Lampridis committed
      The main state machine had an error whereby the wb_cyc and wb_stb
      outputs were not assigned in the IDLE state.
      
      This manifested itself as follows (output from telnet console):
      
      %> writereg 1 100 0 # read to illegal address
        Not acknowledged!
      %> readreg 1 4 # read from legal address returns NACK
        Not acknowledged
      %> readreg 1 4 # next read from legal address returns right data
        Read data: 01234567
      
      The bug was because the first writereg started a WB transfer from
      an unexisting address, threw an error and returned to IDLE without
      releasing the wb_cyc and wb_stb outputs in the process. This meant
      that on the readreg command, the WB write access would still be in
      progress and only on the readreg command, an error would clear the
      wb_cyc and wb_stb, which released the transfer.
      
      The error has been fixed by placing the clearing of wb_cyc and wb_stb
      in the IDLE state.
      46e0f6dc
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